IEEE System Packaging Workshop
South Padre Island, Texas
May 19-21st, 1998
Overview
The East Coast US Workshop of the System Packaging Committee ( formerly Computer Packaging Committee ) was the first away from the US Northeast, and only the second not in the Pocono region of Pennsylvania. The move reflects the increasing activity in Texas, particularly in Austin, and the decrease of the participation of the companies in the Northeast.
For the first time, we saw many of the Session chairs that could not make their own sessions, because of travel restrictions. They did work to build good sessions, sometimes on their own time, but they could not attend. Without this dedication, workshops like this could not survive.
Keynote Presentation by Evan Davidson
Evan Davidson was the Keynote speaker, with the catchy title: "Packaging is the Mouse that Can't Roar." The managers think that packaging should be less than 5% of the cost of the ICs, yet the packaging design provides the mechanical platform and the interconnection design. It is the packaging engineer that optimizes the system, not the IC designer; he is the crucial
line in good system design.
Now, in many companies, packaging is being recognized as the technology that makes the difference between good and bad products.
One measure of the degree of optimization of the packaging design is to count the % of cycle time that is actually used doing something. If there is waste of 10-20% of the cycle time, that is pretty good performance; if the wasted cycle time is 80%, it is time for a better design. System engineers have known this since the days of the IBM 370 system design.
The present managerial perception is that ICs make money, packaging costs money.
Parallel Processor Systems were the white hope of the computer industry in 1993. Then there were a couple of disasters: Excessive cost and software that was not up to the job.
So the industry went back to conventional mainframe / servers, with the change to CMOS effecting major cost savings.
Silicon is not 50% of the area of boards, but it is the silicon package not the actual silicon that should be counted in calculations of packaging density.
When CMOS was slow, packaging was not a problem; but with CMOS at the speed of BiPolar, then performance must be addressed. Workstations were the first to demand good performance from CMOS chips.
MCMs at IBM used to be 10,000 per year, but are now only 1,000, a 10:1 reduction. Furthermore, ceramic MCMs are costly in the first place, and even more so if the capital investment is not used fully. Volume is not high enough to go it alone, the infrastructure must be shared with others to be
cost justifiable.
The MCM is the ultimate package to handle high bandwidth at high frequencies.
What of Direct Chip attach on MCM-L boards? First, Known Good Die testing is needed - but KGD is a myth. The die must be attached to a temporary carrier for burn-in and test, then detached and bonded to the interconnection substrate. That is not Known Good Die, that is formerly good die, or once good die. There is a big difference
The other problem is that direct die attachment requires tightly spaced lands and very very dense circuitry to have the paths wend their way between the bump pads. CSP Chip Scale Packaging is the way to go. The die can be tested on the carrier that will remain with it as it is attached to the board, and the interposer can serve as a space transformer to bring the bump
spacing out to the dimensions that the board manufacturers can easily handle.
Furthermore, for an IBM or a government project, there is a possibility that the system builder can force the IC plant not to do die shrink to maximize their profit. But for the rest of the companies, every die shrink changes the bump spacing and the die spacing, and makes a redesign of the interconnection circuit necessary. The interposer re-distribution layers of the CSP packaging can permit the board I/O bumps to remain constant even as the die size shrinks. So CSP packaging is the way to go for the die on the MCMs.
Session I Bus Architecture Impacts on Package Design, chaired by Frank Ferriolo of IBM who talked of the use of self-timed interfaces in computer design. Of course, the solutions are all digital - he used to design in analog - never again. Of course, more silicon is involved - you might say that they threw silicon at the problem. But the message is that silicon ICs are so low in cost that, if the design is easier or the design time is less, use whatever silicon is needed. It will lower costs in the long run.
Nistala of Sun Microsystems Discussed their Ultra-Processor Multiprocessor Family. The interesting point is that the printed Circuit board is more and more like an MCM, or conversely the MCM is the printed circuit board. It is loaded with Chip Scale Packages, and the silicon concentration
and interconnection line densities are what used to be reserved for MCMs.
This is an increasing noteworthy trend - The Multichip Module is giving way to the Multichip Assembly. Gone is the limitation to the smaller 1 inch CSP and the small 4 chip MCM, and gone also is the 20 chip 4" square MCM. The multichip assemblies may be any size that conveniently packages the system boards.
Paul Everhardt of Silicon Graphics discusses Skew Compensation for the HIPPI-6400 Link. The HIPPI line is an extension of the SGI "Cray Line" with the usual 32 bit microprocessor and micronPacket die packaging. The handling
of pulse transmission is in the management of Skew. That can be done with 4 delay lines, solving the clock delay problem. Jitter is the problem - that makes the "EYE" diagrams blur, or fill (blind eyes). Equalization of the signal is needed, different for every cable length.
Cable is not a limiting factor - even at the 1 Gigahertz frequencies of the system. Transmission is through two differential pairs, with "training" pulses every 10 micronseconds.
Implementation uses Chip Scale Packaging, with wire bonded die.
Session II Telecom / Portable / Wireless Session
Petri Savolainen of Nokia presented the design of their
9000-i Communicator Cellular Phone. This phone was first announced in late 1997, and is being delivered now. People want to carry a phone, read and forward faxes, get access to the internet, and record captured email. There were no all-in-one devices that could do that.
The processor is from AMD, battery life is 35 hours active / 200 hours standby, 1 week with the phone off.
Construction uses 2 MCMs, the first with 7 ICs and some discretes, the second has 6 ICs, 19 discretes. In all there are 13 chip packages, protected by glob top encapsulation.
Why the MCMs? For yield reasons. Putting all this on the board would make for difficult repair and maintenance, but the yield is just better if the core of the system is pre-tested on the MCMs.
Paul Schwab of M/A-COM in a paper with Robert Zappulla of Lucent, presented their work on an MCM RF Switch Packaging. There were 2 identical MCM packages, with a 4 x 6 switch matrix.
The first packaging was ceramic substrate with Berg type clips - making this a leaded chip carrier. Package was not encapsulated, rather the glob top plastic was coated over the die on the substrate. This was dispensed into a "dike" of epoxy, also applied by needle dispensing.
There was little wiring on top - instead most of the signal lines were buried in inner layers to control RFI.
They are transitioning to BGA for the attach to the printed Circuit board.
Hassan Hashimi did the Rockwell talk for Craig Davidson. This packaging was in few-chips MCMs, for Telecom applications. It was a power amplifier, with only a few I/O. It is a co-design, with tradeoffs between the Electrical, Thermal and Mechanical design goals.
The MCMs are thought of as the end product - bare chips are not an end product. It is handled just as if it was a monolithic device. Again, there are small MCMs for yield and repair reasons. Packaging is QFP, PLCC and BGA - a mix depending on the preferences of the customer.
The Seiko Epson Message Watch talk was given by Masuo Kitano. This is the latest attempt to provide wrist watch communicators. The bracelet is the antenna, connected to the internal circuit board by connectors. The connectors were the major cost element.
The circuit board mounts the LCD display, and the display and all chips are mounted using the Stud Bump Bonding technology. Bumps are peripheral at 152 micron pitch.
Two solders are used - one for the ICs and the other for the discretes.
Bill Clark of Delco did the presentation of their Flip chip on Laminate Packaging. Passenger areas of cars have to work at 85C, under the "hold" has to work at 105C, whereas mounted on the engine needs the ability to withstand 125C.
For this reason and others, the boards are not FR-4 but flex on aluminum. How are through vias handled? There are none, the flex is folded over the edge to serve the bottom of the board, with the connections going over the edge with the flex circuit. These boards have to dissipate 12-20 Watts, and the metal core helps the flex tolerate and certainly spread the heatfrom the components.
This is robust technology, and most of it is one side flex only. The technology has a short time-to-market; delivery is 8 weeks earlier than conventional PCB technology. Again, the connector system was 50% of the product value - an unusual consequence of the increasing capability of IC chips.
The last paper was presented by Delco. Board cracking is a function of board thickness. Very thin boards undergo stress from the ICs on front and back that do not pull the board identically. The flex may stretch or bend, but the back side yields to the IC TCEs. I know of one system that worked
perfect when the board was populated on one side only, but the chips cracked when the boards were populated on both sides.
Conversely, very thick boards cause problems because they are so rigid, and the IC chips crack or detach from the boards because of TCE differences, which the board wins because of the strength of the rigid boards.
The worst performance was for medium thin (or medium thick) boards. These were too thick to be compliant, and too thin to be rigid enough to stand up to the compressive and expansion stresses of the chip / board TCE mismatch. Note that other companies have reported the exact opposite - ED
Rick Carbonneau did the presentation for Storagetech on their automotive 2006 System. This was a system built on 100 Nanometer ground rules (0.1 microsecond clock pulse times.) I/O connection to the chips was through 4,000 chip pads; they have not gone to capacitive coupling yet, though I wonder why.
Their MCMs are 1.25mm grid (essentially 50 mil.)
They see C4 coming down from 10 mils to 8 mils now and 6 mils later. They express no concern about the connectivity requirements, yet it is the connectivity requirements that make the cost prohibitive for 6 mil bump spacing.
Session III Microprocessor Packaging;
Mostafa Aghazadeh of Intel talked of their Packaging Strategy. Most of Intel's customers are not very sophisticated - they want Intel to do it all. No underfill for the board attach, do what you have to do on the SCP or MCM.
Intel makes the motherboards to go with the IC packages - sort of do it all and they buy your semiconductors. A high density daughter board is attached to a high density motherboard. The inter motherboards are sold to
companies like Compaq for $15!
Intel uses PGA for their Pentium II package, but is moving to Land Grid array packaging. For the Pentium Pro, the reason for the MCM is the need to closely couple the CPU and the cache. The Pentium Pro MCMs use UNTESTED die, and the lids are sealed. Costs are too high because of the non-existent
possibility of repair.
They plan to stop using custom cache, they plan to use standard B-SRAMs and TAG-rams put into a "cartridge" package. Solve the repair and interchange problem by avoiding soldering.
The boards are FR-4, with copper plate as a back plate heat sink. Vias plated up to form pedestals contact the die and conduct the heat to the back side. This thermal plate is standard Cray technology.
Intel is moving from wirebond to flip chip - because of the faster operating time and lower costs (once the investment has been made.) The substrate, however, is more costly.
Lanxon of Kyocera talked of their Leaded Ceramic chip Carriers for computer applications. This ceramic is green in color and has the usual TCE of 9 - 13. It does have a lower dielectric constant of 5 - 8. Thin ceramic gives worse reliability (cracking); there is a minimum thickness for
reliable products. That is true of plastic CSP packages also, so don't try for the thinnest assembly.
(Note this is the opposite conclusion from Delco in the previous presentation at this workshop!) They tested many underfills, and settled on Locktite Excelon for their use.
Dennis Herrell of AMD discussed their power and cooling strategy for their Microprocessors. New solutions are needed: we must limit surge current "chirping"; i.e., momentary drops in voltage on the bus when there is high activity in the die. Low surge circuit designs are coming in to make the performance more like ECL with its balanced design.
Heat is 30 Watts now, and 50 to 100 very soon. They must stick with air cooling with lidded packages having direct attach heat sinks.
Session IV - Workstations / desktops / portables -
Ray Heald of Sun discussed Alpha Particle tolerant designs. The old solutions were to use pure aluminum, and seal it like a watch. The new realization is that the lead in flip chip technology has significant amounts of U-238 and Thorium 232 particles, which have a 20-year half life.
Solutions: Buy very low alpha particle lead technology. Buy Isotope refined lead, much $$$$$. Use gold solder balls to cut down on the solder, or use gold to conductive adhesive.
Guy Wagner of H-P Corvallis discussed their turbo-cooler Fan. H-P makes fans for sale to other companies - for example this fan is made for Panasonic for their fax machine.
In 1995, the hottest chip that H-P had consumed only 30 to 50 Watts, but now, in 1998 hot chips are running 100 Watts!
The cooling fan unit designed to cope with this heat is a cylinder with a set of vanes set into the rim of the cylinder to control air flow and a turbofan in the center. At 4 meters / second air flow, the differential temperature of the chip to the ambient is only 4 C.
They achieved temperature rise from junction to case of 0.11C/Watt, or 11C.
They tried to use solder columns for lead compliance, but they proved to be fragile under the vibration of the fans. They changed to pressure contacts using fuzz buttons.
Supercomputers, Mainframes, and Servers
Sakamoto of NEC presented the Packaging Technology of the NEC Super Server NX7000/P590. Signal delay limits the permissible bus length, so the packaging design MUST make the system smaller. Even though the system required 1-8 processors and 8 Gbyte of memory, the present design does not
use MCMs, but uses high density Printed Wiring Boards.
The CPU is a 4 chip card, with heat sinks on the back of the die. They are moving to a 528 pin ceramic PGA package.
Haruhiko Yamamoto of Fujitsu talked of their packaging for the Large Scale CMOS Global Server System 8800. Fujitsu is one of the few companies that is still making "Big Iron" the largest mainframes. Everybody thought that these systems would become obsolete with the availibility of workstations
to process at high speed at low cost. They didn't realize that, like payroll data, the internet stored information requires massive amounts of data handling. It is the huge amounts of data that force the continuation of mainframes.
Performance is increasing from 10 Mips, through 50, 100 and now 500 MIPS.
Their technology is MCM, with 10 micron line and space. Each MCM has 2 CPUs, and a 2nd cache. These are big MCMs 128 mm square, the same as used for the BiPolar system designs. The I/O connector is for 936 pins. The substrate is ceramic with thermal vias and 6 layers for the 12 chips.
As many as 2/3 of the total vias might be thermal vias. Aircooling is with a thin plate heat sink, each module dissipates 160 Watts. Interestingly, they reported chip yields (99.7%) and bump yield (99.99998%). Very good!
In a paper by Katopis of IBM on Cool Packaging for the Enterprise System, he stated that the entire system is in MCMs - there are no more single chip modules. The interconnection is a crossbar switch, not a bus.
Technology in the CPU is 1/4 micron; elsewhere 1/3 micron is used. G4 is the IBM alumina technology; G5 is the glass ceramic. The Enterprise design was in G4, and is moving to G5 - the glass ceramic. The polyimide re-distribution layers are 4 layer copper polyimide with 37 micron pitch. IBM Rochester is the center for thin film technology.
Cross talk control can be excellent, if the line width = the dielectric thickness ( for dielectric constant of 4).
Yield after repair is 80%. That used to be 90%, but there is a little less contamination control. The thin film re-distribution layers can definitely be repaired, with well-developed techniques.
Mike Zumbruggen gave the follow-on talk of the IBM Commercial Server Technology. These systems have 12 Power PS microprocessors. In many respects this packaging reverts to older times - the technology is card on board, for example, and the red blinking lights are back. They glow most of the time with the activity.
They once had regulators on the board to give local improvement in di/dt noise; bBut now they find that putting the regulators below the boards and nearer the Power Supply is good enough.
Power supply is two stage, 115AC to 24 DC, then down to the voltages needed for the ICs (1.8, 3.0 etc).
The investment is in funny things. The stiffeners for the cards to prevent warping and misalignment costs more than the card with its 12 ICs and many passives. Weird !?
The last talk by Joe Spano of Sun was a collection of observations on thermal and mechanical design. Acoustic noise was reduced by the use of acoustic foam shot into the inside of the case; EMI was reduced by the use of a special liner; power supplies were hot pluggable, and so were the hard
drives. The delegated the acoustic design to a consulting firm - the job got too big for in-house work.
Conclusions
This was another successful workshop. Talk calibre high, spirit on interaction as high as always - highest on all meetings and workshops.
Attending was a rewarding experience, with the opportunity to mix freely and discuss things with the best system designers in the world.
Condensed by Wulf Knausenberger
from an IDC Report by Jack Balde