CPMT Strategy Emerges
Where is component and packaging technology headed? How can your CPMT society adjust strategy to help prepare members for the future?
Seventeen of your intrepid volunteers addressed these questions on August 28 and 29 in a San Diego hotel overlooking the sailboat gliding harbor.

Ralph Wyndrum, former CPMT President, kicked off the meeting by suggesting that CPMT was not yet aggressively focusing on the future technologies facing our members. As an example, he explained that many of our historical meeting topics were chosen before 100 microcomputers and dozens of micromachines were incorporated in an automobile. Because of the large change that must be made in a short period of time, Ralph suggested that this strategy team identify the top 6 new technologies that impact CPMT members, and form an immediate plan of engagement.

Rao Tummala, Technical VP, presented the new Technical Committee structure. There are 19 TCs, some new and all with enhanced focus. The aim is to help CPMT members prepare for their evolving engineering challenges. (The 19 TCs are listed with the Chairs on page 2 of this Newsletter)

Merrill Palmer, CPMT treasurer, set the boundary conditions for execution of the new strategies. Investment would be made from our existing Society reserves and was to be in the $100K range as voted on by the Board of Governors. The progress in helping our members toward the future could be monitored by counting new members attracted to the Society and attendance growth at meetings as new strategies are implemented. For example, past on-going efforts to financially support CPMT chapters in Eastern Europe have resulted in many member activities and new members.

James Morris, VP of Conferences, pointed out that each of the newly defined Technical Committees have involvement in workshops and conferences. He maintained that our two flagship meetings must be considered the ECTC and IEMT. However, everyone acknowledged that the organizing committees for these meetings often have a life of their own and are not lined up with the TC strategy in most cases. This is a problem that the Board can manage in the future. He also pointed out that the longstanding Lithography Workshop was not supporting the component and packaging lithography needs that have evolved but was caught in VLSI subjects.

Discussion was vigorous on whether there were too many meetings or if the mix of workshops to conferences was correct. Most companies support engineers for 2 or 3 professional events a year; CPMT currently organizes more than 30. On the other hand, our biggest Conference (ECTC) draws less than 15% of our members in a given year. Obviously most members miss any given meeting and some members make none of our international activities. It was pointed out that our large multi-topic conferences were ideal for new engineers and for engineers new to one of CPMT’s historical topics. However, workshops were seen as the way experts met their peers and informally exchanged insight and technology concerns. Everyone had examples of meetings that could be eliminated or merged, but few of our lists agreed. The coordination can start within CPMT, but must be shared with sister organizations such as IMAPS and ASME in order to be effective. Thus any new presentations born of these new strategies must be merged as sessions to already prospering CPMT meetings to stem the tide of ever more gatherings with ever more diluted content.

Madhavan Swaminathan, Chair of our Design TC, discussed the new thrusts. Modeling and measurement of single signal layer lead-frame type packages were being replaced by many layered conductor constructions. Current paths were no longer intuitively obvious so validation of modeling codes was extremely difficult. However, as the designs increase in complexity, accurate modeling is needed more than ever. Although large companies had proprietary software solutions to this, all companies would benefit by CPMT continuing publications and meetings in this area.
Additionally, mixed signal (digital/analog/RF/sensor) designs are often more complex and would benefit from improved design methodology, including software tools and standard test patterns, to allow verification of tools within a design. Madhavan categorized the future needs as follows:

System Partitioning: IC and Package co-design, clock distribution, on-chip vs in package, design verification.
Mixed Design: microwave design, integral passives, quiet island design, EMI, MEMS.
Digital: simultaneous switching noise, power distribution, decoupling, measurements, signal integrity.
Accelerated Modeling of complex design: parameter extraction, fast computation, fast numerical methods, macro-modeling.

Karen Markus, Chair MEMS Packaging TC, challenged everyone to think of microsystems beyond just microelectronics. The term MEMS includes sensors, actuators, mechanical linkages, and electronics…all on a micro-scale. She used the phrase "MEMS merge computation with sensing and actuation to change the way we perceive and control the physical world." Although the goal is often to integrate as much as possible on one chip, cost considerations often lead to 2 chip MEMS solutions given the separate technologies that make each part. Packaging has remained a challenge for MEMS. Most companies use ad hoc solutions for their product, but do not have a way of pooling learned knowledge with the MEMS community. This is a great opportunity of CPMT. MEMS are the enablers that can improve most applications.

MEMS enable about $3-10B of systems today and are rapidly expanding their market impact. Karen listed the following "hot areas."
MEMS for Photonics: fiber aligners, switches, filters, displays.
RF systems: switches, relay, transmission matching, discretes, filters.
Inertial Systems: headmounted VR, GPS, avionics, ordinance, automotive.
Biomedical: implanted system, micro-PCR, fluid handling, drug discovery, microsurgery.
Defense: remote distributed battlefield control, condition-based maintenance, C3.

Today packaging represents 80% of the cost of MEMS components, and the various companies’ development efforts are not building on each other but are disjoint. Challenges such as: "How do you singulate the chips without ruining them with silicon dust?" or "How do you seal them in special atmospheres?" or "How long will they last in the field?" or "How do you handle the 100 volts needed to run the actuators?" are not helping build an infrastructure all can benefit from. CPMT could help provide the technology focus and memory for MEMS packaging. To date packaging is seldom deemed sexy enough to be a university thesis or to be funded by NSF. Although DARPA funds lots of MEMS design and fabrication work, they leave packaging to the vendors. It appears that an international focus could occur in fluidics, RF telecom, photonics, automotive, and military applications.

It was pointed out that keynote addresses, short courses, and a session at ECTC are probably good first steps toward engaging CPMT to its future MEMS packaging activity. It is also suggested that this Newsletter run copy that will get members thinking of the difficulty of packaging these little buggers.

David Keezer, Chair of Test TC, mentioned that test is typically 1/3 the cost of a system. Although there are plenty of IEEE test meetings and publications, none had a focus of package/ assembly testing. Some CPMT focus areas should include:
**KGD (bare chip) testing
**Substrate testing – improvement over flying probe
**Pre-packaging wafer-level burn-in
**Testing during assembly
**Real-time test feedback in manufacturing line
**Test methods for assembled systems
**Non-contact test
**System level diagnostics for ever increasing complexity
**Reuse of test programs
**Mixed signal testing including MEMS/ photonics
A CPMT Test web newsletter was suggested. In addition, putting some of the best papers from existing test conferences (ITC) in our Transaction B would provide a good forum.

Phil Garrou, Chair of wafer packaging, carefully defined this concept. Wafer packaging is building up the package on the IC while still in a wafer format in the back end of the wafer fab. In this way, when the chips are separated, they are already fully packaged. This is in stark contrast with "wafer integration" from the past. One prediction was that by the year 2002 10% of chips will be prepared this way. Most flip-chips are miniature packages with today’s technology. Even small count I/O chips will have wafer packaging. Many of these will use large BGA type balls so they can be mounted directly on PWBs. The large balls allow CTE mismatch without the use of underfill. All this must be hashed out through many CPMT meetings and publications.

Rajen Chanchani, Chair Materials TC, pointed out that CPMT already addresses member needs with several meetings and many transaction papers in this area. However, he discussed the ever increasing need for material properties to insert in computer modeling programs. He suggested that CPMT may be a good focus to provide the database of choice for packaging material properties. There was much discussion on why vendor data was seldom useful for computer modeling. Many databases exist already including the NSF backed one run at Purdue University for SRC (CINDAS) and the recent handbook published by University of Maryland CALCE. It was decided that a more detailed plan of attack was needed before funds were allocated for this activity.

Evan Davidson, Chair of TC14, discussed the 30-year history of this system packaging committee. The initial focus was computer mainframe but has expanded to almost any system larger than one chip. He highly encouraged links between our TCs and other society TCs with similar interests. His TC is joint with the Computer Society. TC-14 supports two workshops a year, one in the US (just occurred in South Padre Island) and one overseas (to be in Ireland during January). The future will involve sharing trade-off criteria for: (1) interconnections on the chip vs in the packaging, (2) organic vs ceramic substrates, and (3) system on a chip [SOC] vs system in a package [SOP].

Doug Hopkins, Chair of Power Packaging TC, pointed out that although every computer has one computational processor it also has at least one electrical power processor. In general power management does not develop its own components and tries to utilize existing packaging in unique ways. For this reason, people outside the power community do not consider it glamorous. However, many systems are now limited by the power block of the design. Future technologies include (1) high temperature operating electronics so the power supply can be smaller and easily reject heat, (2) double sided chip cooling, (3) thermal resistance less than 0.1 C/W, (4) thermal handling capability greater than 1 KW/in2. In addition, the trend to lower voltage IC operation is leading to the need to lower voltage and generate large currents locally in a system…distributed power. Ironically, capacitors have become the lagging component in power electronics.

Paul Wesling, VP Publications, and Dave Palmer explained that whatever the 6 top technologies turned out to be, it was important that part of the member value occur through the new communication technology, the internet. Although only about 5% of CPMT members regularly use the internet today, it is expected that nearly all will consider the web an important daily tool in a few years. Many new services could be provided to members over the web. For example, the keynote addresses on the new thrusts should be put on the CPMT home page as PowerPoint screens (GIF files) with streaming audio from the original presentation. In addition, on-line tutorials should exist for the many members that cannot get to the CPMT short courses. A living glossary of component/ packaging terms was suggested by all those who had been stopped by a new term in a company report. Since terminology expands monthly, a glossary which all members could help enlarge would make us all seem more expert. Paul suggested CPMT buy-in to the on-line transactions system, OPeRA. In addition, we can put our publications back to 1992 on-line for a once-only fee of $25K.
Paul also suggested that CPMT consider using "push" technology. That is, members indicate topics they are most interested in (such as "plastic packages for military," "heat sinking flip chips"…). On a daily or weekly basis, news releases and abstracts concerning their individual interests would be pushed to them through email -- a bit like having a software librarian.
Paul also suggested that each TC have its own website, develop special sections for the CPMT Transactions, and keep the general membership apprised in the CPMT Newsletter.

Harvey Miller of InfraFocus presented his three technologies of CPMT’s future: SiGe, Cu on Low K for IC metalization, and Flip Chip. SiGe wafers are proving 30% less expensive than GaAs and are able to provide high-frequency performance. The packaging challenge is that of high frequency. The trend to copper metalization will change all packaging processes such as solder bumping and underfilling. Once copper begins gaining market share, it will also be necessary to wire bond to copper on low K material. Flip chip is gaining market percentage even in low I/O chips.

Ephram Suhir, Chair of the New Technology Directions TC, presented an itemized view of the growing importance of photonics and related packaging. He also stressed the importance of partnering with the other societies that are very interested in Optical components. "If I were starting out today, I would master photonics packaging , not electronics packaging."

At the end of 2 days of pondering, the following list of technology thrusts was created.
***Packaging of MEMS (sensors, mechanical, photonics, RF, mixed mode)
***Harsh environment packaging (high temp, low temp, bio-implants, displays)
***Packaging of tomorrow’s ICs (Cu, flip chip, high speed, )
***Web education and communication to complement traditional meetings and publications

Immediate action items include;
***Line up plenary speakers and short courses in these key areas for the upcoming ECTC meeting.
***In several subject areas arrange 5+ presentations to make an ECTC session.
***Prepare a Handbook on Technical Committee scope, thrust, resources, and team members
As always, the benefit to CPMT and yourself is through volunteer involvement. In particular, as activities expand, CPMT volunteers in Asia and Europe are needed. Do you understand a new technology thrust that CPMT should address? Can you help carry out the actions? Help yourself, your company, and your profession, contact any of those listed above or Rao Tummala at email: "rao.tummala@ee.gatedch.edu"