IMAPS Advanced Technology Workshop on Next Generation IC and Package Design

July 15-17, 1999 -- Solvang, CA
General Chair: Ronald Bracken, Semiconductor Research Corporation
Technical Co-Chairs: Alina Deutsch, IBM
Madhavan Swaminathan,Georgia Tech
Thursday, July 15
Registration: 10am - 9:45 pm
Lunch: Noon - 1:00 pm

Welcoming Remarks: 1:00 - 1:10 pm
Rao Tummala, Georgia Institute of Technology
Ron Bracken, SRC

Session I: System Optimization - 1:10 pm - 4:25 pm
Chair: Dennis Herrell, AMD
1. System-on-Chip Design Challenges Using Deep Submicron CMOS Technologies, Moises Cases, IBM Corporation, Austin
2. Electrical Design and Evaluation of Organic and Ceramic Flip-Chip Package Technologies for Deep Sub-Micron CMOS ASICS, James Libous, IBM Corporation,Endicott
3. Testing of a Flip-Chip DES Processor, Toby Schaffer, Alan Glaser, Steve Lipa, Paul Franzon, North Carolina State Univ.
4. Development and Applications of Seamless High Off-Chip Connectivity (SHOCC) Technology, Len Schaper, Univ of AR
5. MEMS Technology - Differentiator for Future ICs
Lewis Terman, IBM Corporation, Yorktown

Reception/Dinner: 5:00 - 6:30 pm

Session II: Large IC Design, 6:30 - 9:45 pm
Chair: Lewis Terman, IBM Yorktown
1. Options for Clock Distribution Design Techniques, On and Off Chip, George Geanopoulous, Intel Corporation, Oregon
2. On-Chip Noise Issues Associated with GHz Processor Design, Howard Smith, IBM Corporation, Poughkeepsie
3 . Impact of the On-Chip Inductive Effects on the Power Distribution Networks for Simultaneous Switching Noise and Ground Bounce Analysis for High Speed Processor Design
Ersed Akcasu OEM International
4. A Wide Range of CMOS Adaptive Output Drivers for Customized Control of Signal Rise Time and Power/Ground Noise, Joungho Kim, KAIST
5. A Novel Radio Frequency Clocking Scheme for Over GHz Digital Two-Phase Clock Distribution,
Joungho Kim, KAIST

Friday, July 16
Breakfast: 8 - 9 am

Session III: IC and Package Test, 9:00 - 11:40 am
Chair: Paul Franzon, North Carolina State University
1. IC Packaging and Test, Arnold Frisch, Opmaxx Inc.
2. Noninvasive Picosecond On-Chip Circuit Timing Imaging Using Backside Time Resolved Photoluminiscence
Pia Sanda, IBM Corporation, Yorktown
3. Defect Detection in Package Interconnections
Arnold Halerin, IBM Corporation, Yorktown
4. A Survey of Test Methods Being Developed at Georgia Tech.
Madhavan Swaminathan, Georgia Institute of Technology

Lunch: Noon - 1 pm (Afternoon Free for Networking)
Reception/Dinner: 5 - 6:30 pm

Session IV: Modeling and Simulation Techniques
Chair: Joungho Kim, KAIST, 6:30 - 9:10 pm
1. Simulation of High-Speed Interconnects Using Multilevel Model-Reduction Techniques,
Michael Nakhla, Carleton University
2. Reduction Techniques of an Advanced Package Structure
Zhen Mu, Intel Corporation
3 Frequency-Dependent Losses on High-Performance Interconnections, Alina Deutsch, IBM Corporation, Yorktown
4 Simultaneous Switching Noise and Power Plane Bounce for CMOS Technology, Larry Smith, SUN

Saturday, July 17
Breakfast: 8:00 am - 9:00 am

Session V: Optical Link Integration, 9:00 - Noon
Chair: Ray Kostuk, University of Arizona
1 Optoelectronics Flip-Chip-Bonded to CMOS VLSI Circuits
Ashok Krishnamoorthy, Lucent Technologies
2 Embedding of Polymer Optical Fibers for Board-Level Optical Interconnection Application
Yao Li, Jun Ai, Jan Popelek, NEC Research Institute
3 Photonic Interconnect Solutions to Electronic Data Transfer Problems, Ray Kostuk, Andreas Cangellaris, Univ. of
Arizona, Univ. of Illinois
4 Exploiting the Advantages of Free-space Optical Interconnections in Multiprocessor Systems
Michael Haney, George Mason University

Closing Remarks: 11:40 - 11:50 am
Madhavan Swaminathan, Georgia Institute of Technology