Austin Spring Workshop of the System Packaging Committee
April 14-16, 1999
This is the latest of the Workshops of the Systems Packaging Committee of the IEEE, formerly the IEEE Computer Packaging Committee. It was the 43rd workshop of the Committee, and the 4th under the co-sponsorship of CPMT, Technical Committee 14.
Attendance was moving back up after the problems of the South Padre Island Workshop. 84 attendees this time, a nice recovery. John Segelken and Nick Teneketges were the Program Chairs, Moises Cases the General Chair.
Session I Power and Noise Management, Eric Bogatin
Clint Walker of INTEL discussed the use of the ANSOFT4T and the PSPICE modeling tools with respect to a design for a microprocessor for a vacuum cleaner. The microprocessor controlled 15 Ampere 110 volt supply, and had to cope with 2 V sudden drops in the IC voltages. The goal was to reduce the transients to under 50mv transients in the 1.0 Volt supply. They modeled a mesh plane in FR-4 5.5 mils thick, and compared it to BCB of under 4 mils thick, which was better.
Rick Evans of SGS Thomson talked of the Performance of their BGA Packages. These are designed to transmit 100 MBytes of data. The package was BGA, cavity down, and the protection was overmolding. (Glob top was inadequate) Going to a BGA reduced the average trace length to 0.9mm by tolerating bumps under the active portions of the chips.
They like electroplating of the interconnect - while electroless might work, they don't trust it. To go to full flip chip at this time is definitely more costly, and seems to offer little, if any, performance advantage. (Wirebonding is hard to kill.)
Ben Becker of the University of South Carolina talked of Power Distribution for High Performance Processors. It was concerned with the design tradeoffs in the use of decoupling capacitors on the chip, on the package, and on the board. The alternatives provide choices between complexity and performance.
Lumped models are ineffective in predicting performance; rigorous field-based analysis models are much better. But they are computation intensive. Conclusion - distributed elements are better.
Construction was a limited 3D stacking, in a simplified version (unspecified). Dielectric for the capacitors was PZT, deposited by sol-gel technology. Dielectric Constant was 1,000, giving 2,000 nF/cm sq. TCE was quite near that of Silicon!
Jeff Cain of AVX discussed the Advances in Passive Components, and the Effect on System Performance. Sizes of 1 microF to 4.2 microF. Technology is 3.4 microns thick film layers for the 4.2 microF capacitors (phenomenally very thin), and it is not surprising that most shipments are for less than 4 microF.
Tantalum capacitors have been dropping series resistance; good units are down below 65 milliOhms. A joint development with IBM is to produce bumped capacitors suitable for flip chip bonding.
Why continued interest in better capacitors? Because top of line future chips consume 100 Amps for durations of 1 nanosecond, which can result in di/dt noise of over 500mVif not properly isolated with decoupling capacitors.
603 type capacitors are 1 cent each, and 100,000 are made per day, or 36 Million/year; a $360,000 business.
Dave Quint of H-P asked "What is Ground Bounce?" The thrust of his talk was to stop worrying and trust your ground constructions. Specifically, splitting grounds can reduce ground bounce. Series inductance is important, and must be controlled, but most people do not realize that the calculated inductance is NOT realized if there are nearby grounds.
Putting in an "idle" ground, changes the inductance, and the inductance has to be recalculated. The inductance carries the energy in the surrounding field, and bringing up a ground plane, changes the field. But the "idle" ground improves the performance of the decoupling capacitors.
Inductance is a function of the geometry of everything else!
Invited Featured Talk - Hiroshi Go of Hitachi, Kanagawa
Hitachi is the manufacturer of the Enterprise Server RISC Computers. These are 128 node machines, operating at 1 Teraflops. Each processor module uses 600 Watts, and has discrete surface mounted capacitors for the major decoupling capacitors. Finned heat sinks are used on each chip, dissipating 45 watts. The module has 7 metal layers, 24 million transistors, and is C4 attached to the Board Substrate with 12,864 bumps!
This is the construction we have seen before - the LSI chip is C4 bonded to the carrier module, and the lid of the module has projecting fingers. These intermesh (but do not touch) similar fingers of an over-lid that has the heat sink.
The space between is filled with light oil, permitting heat transfer between the top of the lid with the heat sink, and the bottom of the lid attached to the chip substrate, with the oil filled gap coping with the TCE differences of the heat sink and the Glass Ceramic.
The system requires 9 air conditioners, consuming 423 Kilowatts. Heat output is 198KWs. There are 192 discrete capacitors, and 536 capacitor arrays.
This is single cycle synchronous transfer stuff, operating at 250MHz on a single line, and 750 MBs.
Session II Communications and Wireless - Sullivan and Abdelgany
Multichip Modules for Commercial Wireless Applications, a presentation of Joseph Adams of Conexant Systems, was a discussion of making MCMs in a 6 month cycle time. These modules were in small package formats, using GaAs and Silicon CMOS and bipolar chips for digital and analog circuits. Passives were integral.
Construction was MCM-L, with 4 chips, package price (not cost, price) was under $6. Package alone without the chips was less than $2! Production was 1 million per month, $72 Million product shipped per year.
No burn in - discard the rejects (Yields were greater than 95%). The substrate was BT laminate, with blind filled vias and the die was connected by wirebonding. Protection was overmolding.
This is technology chosen for standard manufacture - all tried and proven elements. A very practical approach.
Advantages of these MCMs were:
o A complete unit subsystem used in multiple products
o Mixed technologies, not possible with system-on-a-chip
o Short design times, including instant prototypes
o Less passives if the interconnect is well controlled
FR-4 could do the job, they just thought BT was a little more forgiving in processing. A great talk showing how standard MCM technology has become.
Tohru Kishimoto of NTT talked of High Speed and Density in Telecom Systems. He stated that the previous designs were not extendible, and new approaches were sought. They are working with 4 companies for their Hi-Pas (High Density Packaging Systems) development effort.
The whole system was described, including the use of a programmable back plane for the various variations of the design. They aimed at sub-Gigabit signal transmission.
Len Alton of Unisys did an update on his Custom Socket design for a 1089 pin Leaded grid array package. This is connected using Cinapse fuzz buttons in vias, with the pins of the packages connecting to the board by pushing the pins into the fuzz-button filled holes.
Update information was that co-planarity has proved to be VERY important - co-planarity must be better that 0.006 inches.
But Unisys abandoned CINCH and went to a Thomas & Betts metallized polymer socket. The problem was that some of the fuzz buttons fell out of the via holes. If the assembly floor is carpeted, the operators had to search the floor for fuzz buttons, AND THEN TRY TO FIND THE VIA HOLE THAT HAD LOST THE BUTTON! (Very time-consuming)
The module is held to the board by corner screws, but if there is a bow in the substrate, connections in the middle would be poor. A Belleville spring modified to an "X" shape was included between the module and the heat sink, which enabled the center contacts to be adequate if the board warp was less that 7 mills.
Session III Advanced Packaging and High Density Interconnects -- John Nelson and Courtland Robinson
Len Schaper did a talk on Advanced Interconnection. This was a SHOCC talk - the Off-Chip Connection technology pioneered by Schaper and a consortium of companies.
The advantage of putting the longer lines in copper on the substrate, and removing them from the chip design. This permits breaking up the larger chips into smaller chips, without loss of performance, even improvement. Technology is 10 microns line and space.
Interconnect density is 1400 cm/cm sq, compared to only 400 for the usual MCM.
Any interconnect lines over 2mm long has lower delay if off the chip than in the substrate. The problem is to get the silicon manufacturers to omit all the long leads. They want to sell the idea of bigger chips, and system-on-a-chip, but the better performance would happen if they took the long interconnect lines off the chips and made SMALLER chips. A big problem in opposing goals.
There is another detriment - you can't test the chips as bare chips - the circuits do not work unless they are assembled on an interposer or interconnect board, rigid or flex. The testing can then be done - conventional testing, but with connectors that can work with the Single Chip Package.
Evan Davidson of IBM talked of the comparison of Large chip vs MCMs for High performance Systems. This is SOC - System-on-Chip packaging versus SOP System-on-Package. The SIA roadmap predicts system on a chip by the year 2012- on a chip 70mm square, operating with a 10 GHz clock speed.
No way! It isn't going to happen. Looking at trend lines is a dumb thing to do - density cannot just go up, there are some basic laws of physics that prevent that.
So why do so many people from so many companies make statements about these phenomenal high densities thought to be possible? It is the young guys who realize that is what the management wants to hear, and they better say that if they want to keep a job. No experienced person would be caught in such a prediction. (Evan's words, but I agree, JB) The question of whether we can reduce scaling by 30% per year should be one of cost. Is this increase in density cost justified? So Multichip Modules are here to stay.
He repeated the data on delays of up to 10 times if long lines are in aluminum on the chip surface. Rather than using SHOCC copper on substrate techniques, IBM is trying copper interconnect metallization on the silicon chips. It can be done, but there are 9 or more layers of metal involved, and the differences in TCE from silicon causes concerns about delamination.
Far better to break up the chip to 4 small chips, mount them on an MCM, where all the long lines are in the copper package.
Are there big cost advantages? No! A single 400 mm sq chip in a package might cost $1350, and a 4 chip Multichip Module would be $1,200; not a big cost gain. But the yield and performance advantages are compelling.
But the silicon guys say you cannot break up the big chips and get good performance. They are wrong - even though they fight it, 4 smaller chips will out-perform a big chip every time!
Tim LeClair of Nanogen talked of Flip Chip Interconnection for DNA devices. This was the reach-out presentation of this workshop.
DNA detection has been fully automated. No more looking at chromatographs. Put a sample on an agar plate that has been premixed with the DNA to be matched. Fluorescent light binds the sample to the surface, and a subsequent reverse bias repels the loose particles and junk.
IF THERE IS A MATCH the DNA material glows under the fluorescent light.
Very impressive. He showed an agar dish on which he had lightly dragged a needle to deposit similar DNA material in the shape of a "W". Look at it with fluorescent light - a bright red "W". Use somebody else's DNA, nothing. This natural bonding of DNA strands to others is faster than any possible analysis method. Mother nature is the winner here.
The results are visible in 5 minutes, and automatic sensors can print out which samples have DNA matches.
Of course there are some additional needs - to meter out a standard amount of DNA, integrating a controlled MEM pump element, and the package with the detector needs to be sealed to contain the materials, yet have an open space to permit the moving parts of a pump to work.
Gary Weihe gave the Sheldahl talk on Flex Circuit Packaging for TBGAs and CSPs. This is a double-sided 2 mil tape, 330 mm wide. 3M is developing the same capability. IBM Endicott's Flex Line has been sold, and will enter this market soon. Line widths are moving to 25-30 from their present 50 microns, Line and space is moving from 37.5 to 30 to 25, and Vias are already 25 microns.
Die sizes are presently limited by pad pitch of 50 microns I/O. If the flex interconnect substrate is less than 50 microns, smaller vias are possible. TI has a MicroSTAR package, Tessera has their MicroBGA, Amkor has Flex BGA. There are also flip chip TBGAs coming on the market. Costs are 0.5 to 1 cents per lead.
These are not packaged in molded plastic alone - that is not adequate to dissipate the heat of the new chips, which might be 100 Watts. Rather Sheldahl supplies the tape with a copper heat spreader backing, all the customer does is attach the chips, wirebond, and encapsulation.
Circuit impedance is 55 Ohms, with little cost premium. Most applications today are for 432 leads, with Sheldahl demonstrating 672 I/O with their TBGA. Prices are around $8 to $9 per chip package.
Bill Baker, former Rockwell President, did an Overview of the state of IC packaging, called "Critical Factors for HDI Packaging. This was more than the usual trite listing of all the needs of the technology, it was an assessment of the potentials and acceptance. Let me quote:
1.- There will be no silicon size shrink. If higher density is possible, more will be required of the chip.
2.- There will be no silicon size increase - MCMs make the performance better with present size chips.
3.- SHOCC is not in play - use the Evan Davidson utilization of copper for the interconnects without removing aluminum metallization interconnect from the chips. It is too difficult to ask for testing only after assembly to an interconnect substrate.
4.- Few companies now do co-design, but co-design is needed and inevitable.
5.- More lapping / grinding of the chips will be done to reduce thickness and the thickness of packages (See the paper at the ECTC by 3M - JB)
6.- Wirebonding is not dead, nor dying. It is the best way to go for reduced time-to-market.
7.- Chips will be sealed at the IC factory - Silicon Carbide over Silicon Nitride. ) Performance is almost as good as silicone gel, but the process is done at the IC factory, not by the assembler.
8.- Pad seals are in electroless Nickel (Fraunhofer) not aluminum.
9.- Wafer scale packaging makes the use of SHOCC and the inclusion of passives more difficult. But there are major cost advantages.
Don Hunter of JPL made some relevant comments after his talk - (I have grouped them here with Bill Baker's comments - JB) He discussed the expected growth of wireless communication to a 153 Billion dollar business by the year 2000. Most on that is 900 MHz spread spectrum, but the Nokia project Bluetooth for satellite communication, with its 10 meter omni-directional antenna is important. Design is RFID, with no batteries. It will process the energy from the satellite and reflect the signals back to the satellite.
10.- PCs with 2GHz spread spectrum handset costs are down to $138. Schaper commented that ALIVE boards serve 50% of the PCS market.
11.- Gallium Arsenide will displace Silicon for Power supplies! (I had not been following this development - perhaps you have not either, JB)
Ken Relich talked of Focused Ion Beams to effect connections and modifications. The technology can cut lines, can deposit new lines, can cut vias to the other side of the interconnect, and connect to other side paths.
Like the laser programmed re-work of the IBM backplanes in the 70's, there is a limit to the amount of rework to be done to a circuit when it is better to re-do the artwork. For the present, it is the experience of Unisys that up to 40 connections can be broken or made and still be economic compared to re-doing the artwork of the chips or circuits. Tungsten can be deposited and seems to be more robust than Platinum.
How to change a chip interconnect after assembly face down? Drill through the chip from the back side, and cut the surface lead from underneath! Make the new connection the new way. How do you do that? The registration of the circuit must be perfect to cut a blind via from the blank backside and hit the target with spacings of leads at the 10 microns of IC manufacture!
Session IV The evening session on Military and Space Packaging -- Don Hunter of JPL
Lincoln High Density Radar Receiver was described by Dave Johnson of Lincoln Labs. This was a useful comparative technology talk: implementing MCM designs in MCM-C, MCM-L/FR4. MCM-D/HDI. and MCM-L/TMM
The MCM-C was in low temperature ceramic by Scrantom Engineering, with integral passives. Some of the ICs, however, were packaged because bare die were not available. Assembly was done on the big substrate, and then testing, all done before die punching or sawing.
Cooling was by heat pipes, using ethylene glycol and water for the liquid medium. New aircraft now have liquid cooling systems on board, so the heat pipes to pump the heat someplace else can be eliminated by direct connection to the aircraft liquid cooling manifold.
Connectors are needed for the mixed signals to be transmitted - a modified Amphenol Connector and a Gilbert floating coax connector seemed to work. Pioneer did the connector for the flex circuits. Gone are the days when AMP was a major player in new technology.
"COTS" Re-packaging of an SGI/Cray Supercomputer for the Navy AEGIS Application - Jeff Palmer did the presentation. The buzzword is COTS, for Commercial Off-The-Shelf parts and components. The requirement is that the computer survive 150 G Torpedo shock test! The connectors support the card weight, so a frame was needed to pass the torpedo test.
New isolation was required on each card as it got installed in the frame. The whole frame was supported by big isolators - I mean BIG! Seven inches in diameter, and a foot long!
Don Hunter of JPL described their Integration of a 3D system on a Space Craft Panel for the Integrated Avionics System. This is a stacked assembly, with no possibility of changing a card in the stack. Replace the whole module. If possible interchange of cards is expected, they use horizontal multichip module
technology. They developed the architecture for "System-on-a-Chip" but ended up by using many substrates or CSPs.
Dale McKeevy of Pioneer Circuits spoke of their use of Rigid-Flex designs. This was a 36" long 6-layer flex used in the Mars Pathfinder. It survives 600,000 bend cycles if the bends are not too tight. The boards were acrylic, with no vias, and no expansion problems
Sessions 5A and 5B - Workstations, Portables, Servers,
-- Katopis and Novotny
George Katopis did the GEMI MCM design for their new mainframe - server. This is a 12 processor system, with performance over 1000 MIPS. Processor speed is 600 MHz - and there is good off-chip design running at 300 MHz to support that. Design cycles were once 4 years - now they are down to less than 1 year (6 weeks for the design! ).
The internal switching is a simplified non-blocking network.
The MCM is glass ceramic, 75 layers, 34 signal layers. Interconnect wiring on one 5" square is almost 600 meters.
Performance data shows delays 42% in the chips, 43% in the interchip wiring, and 15% skew and noise.
If there are offending leads for noise reasons, those leads are moved to the bottom plane and located there. That plane is reserved for such leads.
The high performance interconnect is in the 6 layer thin film interconnect in this MCM-D/C construction. Thin film is faster than ceramic by a factor of 3 for lines less than 80mm.
Noise control capacitors are used for different noise frequencies:
Low frequencies - electrolytics and ceramics on the board Medium - Over 100 nF on the MCM High - 200 nF 1/2 on the chip and 1/2 on the MCM
Hanna of IBM talked of 8-way SMP, and Standards. The SMP systems of IBM are basically a big personal computer. Architecture is INTEL Profusion. (The architecture developed by Corrolary - Intel bought them. JB).
Nothing special - line impedance was 65 Ohms, signal layers are 1 oz copper.
Belady of H-P talked of the industry needs for liquid cooling. With individual chips dissipating up to 100 Watts, air cooling can not do the job. But nobody wants to hear that message. Existing data centers can handle 40 to 70 Watts/.Sq ft with an 18" raised floor. Future needs are for 125 W/sq ft
But few rooms can handle the air flow even with an 18" raised floor, because there is a universal tendency to leave old cables in place when changing systems, and just put the cables for the new systems right on top of the old. (The System people think the raised floor is for cables) Kobayachi-san indicated that Hitachi is specifying 36" raised floor for this reason!
There is another problem with cooling from the under floor space. Adjacent machines IBM or others, also consume power and need cooling air. The discharge from these other machines reduces the cooling available to the machine under investigation. Each new system makes the heat problem a little worse, and eventually it is 55C in the room!
Fixes:
1.- Space the machines out (not popular)
2.- Provide air supply from the middle (not popular)
3.- Reduce the performance (not acceptable)
4.- Blame the other guy (Yeah!)
At the moment people would rather blame the other guy than fix the problem.
The big problem is that there are two organizations, the computer manufacturer / user, and the building that provides the cooling. Liquid cooling is twice as effective, space is smaller and no finned heat sinks are needed. The resultant system is smaller, so the computers are simpler. Furthermore, no use is made of the raised floor for cooling.
The customer is part of the problem, but the computer manufacturer is ultimately responsible for the problem. THE CUSTOMER MUST BE TOLD THAT HE HAS TO PROVIDE LIQUID COOLING IF HE WANTS THE PERFORMANCE OF THE NEW SYSTEMS.
Bill Hamburgen of Compaq (formerly DEC) had a catchy title; "Itsy bitsy computer Packaging:" These are small, light PCs with a performance that of a 2 year old desk computer. The Compaq design has a one piece rigid-flex motherboard, and 160 I/O BGA and MicroBGA packages. The unit can be upgraded with PCMCIA cards, planned from the beginning. A tiny speaker is provided by using a hearing aid eyeglass frame speaker. Batteries are 3 AAA, Lithium cells are best.
If a function is not of interest to ALL users, do not make it part of the system - add that function with a PCMCIA card.
Local voltage regulation helps even in such small boards (surprise). The regulator is put beside each unit.
Design experience:
3 of 5 connectors were bad
2 of 5 switches were bad. Side loads on boards and packages were a problem
They therefore chose their companies VERY carefully.
The talk by Prasenjit Ghosh of INTEL was on Power Dissipation. He said the main effort should be to lower the power needed by the circuits, not finding ways to dump the heat on someone else in the aircraft or in the room.
Joel Dietz of Compaq talked of Alpha 1st level packages. The big and continuing problem is that the silicon guys do not want to talk to the packaging people, but finish their designs and push them over the wall. Sound familiar - Packaging engineers have been saying that for 30 years.
The Alpha package is wirebonded into a 4 chip PGA ceramic package, with at 67 microns wire pitch. The combination works to 150MHz. Present pins are 587, future Alpha chips will need 1440! For higher performance, the decoupling capacitors on top of the chip will have to increase from 2.3 microF to 3.8 microF!
Samsung and Intel are the foundries, the packages are both glass/ceramic and alumina. The new layouts do not permit die shrink without complete re-design.
Pins are used because they support 1 pound heat sinks! No BGAs or microBGAs are used.
Conclusions
This was another successful workshop, with attendance climbing to normal. This was the last workshop under Evan Davidson as Committee Chair. The next chair will be Lisa Palotti of H-P. Len Alton will be Workshop chair, and John Segelken and Nick Teneketges will do the Program Chair roles again. Location will be Indian Wells (Palm Springs area) the first week of May. Look for it on the Web Site.
--Abridged from an IDC report by Jack Balde
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