Packaging Show to Highlight ‘Silicon-to-System’ Packaging Integration Solutions
PackCon, an exposition and conference focused on the silicon-to-system integration of advanced packaging technologies, will be held October 2-4, 2000, at the Santa Clara Convention Center, Santa Clara, California.
The exposition, which runs October 3-4, is presented by Semiconductor Equipment and Materials International (SEMI) and the Microelectronics Packaging and Test Engineering Council (MEPTEC). In conjunction with the exposition, the 25th IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium will be held October 2-3.
PackCon replaces the Chip Scale International (CSI) show which focused on chip scale packaging technology. The new exposition has been refocused and expanded to include full ‘silicon-to-system’ packaging and testing solutions, a recognition of the expanding breadth of new packaging and testing technologies.
"The issues and challenges facing semiconductor packaging and testing are no longer the sole domain of the back-end, especially as new packaging technologies have moved towards front-end processing," said Stanley Myers, president of SEMI. "The increasing demand for greater miniaturization and density in today’s chips and electronics is driving advances in packaging and test and it is critical that we address these developments as they relate through the entire manufacturing process, from the wafer to the completed system."

For information on IEMT or Packcon see web site at http://www.semi.org

SEMI press release excerpt