The 2000 Hikone, Japan Workshop of the Systems Packaging Committee January 23-25, 2000
Excerpt of an Interconnection Decision Consulting Report
Background
This was the seventh workshop of the Japan Committee, and
the first to be held in Hikone. (The first three were in Oiso, and the next 3 at Tsukuba.) It was the last of the original cycle of sponsorship by the 7 company responsibility ( NTT, NEC, Hitachi, Fujitsu, OKI, Toshiba and IBM Japan ). Yutaka Tsukada of IBM Yasu was the General Chair.

Keynote Presentations
Emanuel Crabbe of IBM approached packaging from the chip side - focusing on the changes in chip technology as they influence packaging and system design. He firmly believes that the number of elements per chip will increase, but he admits, reluctantly, that performance speed will suffer. He sees the trend to lower voltage for the ICs, but if the voltage is lower, the threshold is lower, so future circuits will be extremely noise sensitive.
Two threshold voltages will be required - with the second
or lower voltage used for critical paths. 2 micron wide copper
should be preferred for long lines, but 1 micron will work.
Aluminum has 2 1/2 to 3 times the resistance, and is no longer
suitable at very high densities. Linewidth of 55 NM ( I still
prefer microns - 0.055 microns )
What is notable ? An avowed big chip system-on-a-chip
advocate, he admitted that performance suffers if everything is
on one chip. and that such big chips are VERY costly.
Larry Moresco of INTEL DID A TALK ON: SMALLER, CHEAPER, FASTER:. The philosophy is to achieve "Just-in-time" capability, and to use sockets for the ICs ! Furthermore,
design the BOARD first, determine the I/O, THEN design the chip.
Packaging semiconductor circuits can be
LSI Centered - take a known chip design
Package Centered - Assume a package is known
Board Centered - fit the chips to the board.
Direct Chip Attach provides the means to adapt the chip to
the board. There can be a single chip CPU, or there can be a
multichip module in a package.
They use some PGAs in ceramic for surface mount, but use
more BGAs in molded packages, with molded-in heat sinks. If the peripheral die can be small enough to get into the allowed space on the board, use it, but the default is a BGA to get the
footprint into the required space.
OLGA - Organic Leadless Grid Array uses 50 mil bumps on the board - used for the CPU for Mobile network equipment.
Substrate is FR4 but also BT Resin, interconnect is Copper /
polyimide. Biggest problems were alignment and fabrication
yield. Footprints are "standard" All packages made equivalent
to the IBM flip chip array standards.
Pitches for I/O at 25 micron have costs of $ 1,000
Pitches for I/O at 150 micron have costs of < $500
only 200 micron or better can cost only $ 200

To get the lower cost, use bigger pitch, or use wafer
stacked chips in BGA packages. If pitches are 30% larger, but
stacking is used, the assembly is 80% smaller. Cost is 1/2.

For stacked chips, BOTH flip chip and wirebond are used.
The bottom chip is attached using flip chip technology, the top
chip is wirebonded to the substrate. No through-the-silicon
vias, but no congestion at the wire bond pads either.
Why not use something 4 X bigger - 100 micron, because it
is cheaper ! DON'T SPEND ANY MONEY TO DRIVE THE PITCH BELOW 100 micron.
Substrate costs INCREASE with smaller I/O pitch
Die Costs DECREASE with smaller chips and I/O pitch

Seek the minimum ! Do not let the IC guys reduce their
costs at the expense of the packaging cost. At the moment, the
cost minimum seems to be at 100 micron ( 4 mil ).
Bob Guernsey of IBM is Director of Silicon Technology
Strategy for IBM. He was the perfect person to discuss the
Affordable Information Transfer Technology.
Electronics technology will reach $ 10 Trillion by the year
2026, and be 10% of the world's economy. Gone forever are the
days when automotive manufacture was the standard of
manufacturing capability and employment.
User applications like the Sony Playstation II, WebTV, Palm Pilot and others are exploding into consumer's hands. Only 16% access the Internet from their PCs; by 2002, that number will be 50%. The trend is to continuous interconnect with the INTERNET; The Palm Pilot already offers that, and the phone companies offer DSL.
All sorts of equipment will have internet capability with
their embedded microprocessors - some of them silly. Why one
would want to remotely control a toaster is unfathomable.
Smart Networks will go from LANs (Local Area Networks) to WANs ( Wide Area Networks - in some cases the whole world. The memory storage capabilities are overwhelming, the number of servers massive, the change in the hardware tremendous. Part of this worldwide availability of information is the ability to order for instant play any movie ever made since Hollywood started in the business - in color and real time, with pause and rewind capability in case the doorbell rings while you are viewing. Imagine the pixels to be stored - much more than
trillions. ( I think it is time to re-use the mathematical Googol. 10 followed by as many zeros as you can write before your arm falls off ( Look it up ! ).
Server Systems - Deep Computers. This is the fastest
growing part of the electronics market, and data has already
surpassed all voice for the telecom networks. ( By the way,
cellular has already surpassed all wired phone installed from
the start of telephony.) The growth rate for servers is 54%
annual, for $ 5 Billion in 2003. Hardware capability takes over
from software as the dominant driver. It is perhaps easier to
de-bug, it reduces staff, and is much more efficient, therefore
cheaper.
Hard drive capabilities using magnetic storage doubles every
22 months. Improved cooling increases performance by increasing operating speed. This may be the death of simple air cooling. Liquid cooling is being considered part of the system, not the responsibility of the building engineering department, though some heat pipes and local refrigeration are being used as
alternatives.
Optical interconnect is needed for all large systems, using Erbium-doped fibers. Will MEMs be used for Optical switching? Guernsey was not yet aware of the possibilities. Will Optical go all the way to the home ? Probably not.
Optical technology might not make it to the home, as part
of the Telephone network, but it will make it to home inside of
the system boxes at the servers and in the mid-sized computers.
Cable technology delivers to the microprocessor more and
more data, for example as TV connection and Movies. The cache on the microprocessor chips need to be bigger and close to the logic chips, merging the two technologies.
In big systems like these, density is more important than cost. Here system-on-a-chip may find it's application, not in PC and personal computers or telephones.
NUMA - Non Uniform Memory Access will be used with up
to 100 microprocessors. Most destinations are nearby, therefore
faster.
We need cheaper ways to service equipment.
IBM next generation Scalable Processer Server has 1000 X
the capability of Deep Blue - the one that won the chess
championship. Construction is 32 microprocessors PER CHIP! 64 chips to the board, 8 boards to the rack, 64 racks per system -
over 40,000 square feet.
Die size will not shrink. If it is smaller than now, either there is no room for the pinouts, or the cost is too much. Instead the trend will be to add the drivers, the cache and the passives to the chips, and the ability to process mixed signals. Voltage regulators can move to the chip, and capacitance also.
We all know the crossover curves between lowering IC costs and Higher interconnect costs with increasing density. The composite curve is saddle shaped. The reality is that the saddle of the cost minimum is moving out toward higher density. Not a revolution, but an evolution.
Systems-on-a package will be more cost effective than
system-on-a-chip. The challenge is to use low cost MCMs in high performance systems. ( 4 to 6 chips not 300 ) Perhaps the
only way is to integrate all design organizations into one -
providing payoff for the best design, not the sub-optimum of the
best design to meet the desires of only one of the players. Good chip design is not enough, good packaging design is not enough, Good co-design is a must !

Session I High Performance Systems
George Katopis gave an update on the IBM CMOS G6 sixth generation server. Generally there was not a major change in technology, just important evolution of the techniques reported previously.
Koyano of Hitachi presented the packaging for their Skyline Trinium System For cooling, Hitachi now solders the chip to an Aluminum Nitride heat spreader plate which is soldered to a plate that is coupled to a water-cooled heat exchanger.
The rational for the construction is the huge temperature
differentials at the moment of startup, accompanied by some bi-
material bending. One way to reduce that is to turn on the
computer step-by-step, or to increase the conductivity of the
heat sink, and of the base.
Improvement over the previous system was 40% - 4000 MTOF
The Fujitsu talk was by Suzuki, on their high end computer. The ICs were in 50 mil PGA packages, with a high conductivity lid bonded to the tops of the individual chips. Heat fins were attached to the thick lid . ( He didn't name it, I assume it was either Aluminum - Silicon Carbide or metal ) C4 pitch was 6 mils, and thin film lines were 5 micron wide on 12.5 micron pitch.
They used chip area array connectors for up to 10,000 bumps! Again on a 6 mil pitch.
Evan Davidson talked about the IBM RS/6000 SP Packaging parallel processor technology. The large web server business is developing slowly, Advanced Super Computer Initiative is developing two models, ASCII Blue is the commercialization of the Big Blue Computer that won he chess matches, ASCI White, is the scientific computer for the next generation.
They need and have developed a big X-Bar switch. They
solved the blocking problem by having huge buffers that store
data if the preferred path is busy, releasing it later. SCMs
are used extensively, and are mostly cheaper than other solutions, but single chip packages are used also for big bandwidth applications.
IC feature size are reduced using X-Ray lithography - which
they not only use for IBM products, but have sold the technology for use by Apple computers.
Memory storage boards are given BIST testing, then stored
in inventory - there is no active testing.
Tanaka from NEC talked of their SX 5 Computer.
Construction is Multi Chip Packages into sockets on the boards. There are 16 CPUs on each board, in two stacks 8 high, for a total of 16 million transistors per CPU.

Thermal and Noise Management
Dave Souma of POWER DEVICES discuss the characteristics of phase change cooling methods.
Thermal flow from the MCMs and packages can be to copper, but it is too heavy. The differential expansions are handled with close proximity, with light oils and some greases.
( Silicone based greases are banned ) Phase change is also used.
But basically, the final step of heat removal is the end of the
chain - increasingly using phase change materials.
Above 65 C paraffin works best; it can be metal oxide
filled. The interposing heat film between the die package and
the heat sink is only 1/2 mil thick.
Similarly, the presentation by OKI of their Electrical Noise technology also seemed state-of-the-art, but in a sense what one would expect. Everybody is concerned with noise control, it is just that their implementation is quite good.
Len Schaper presented their floating plate decoupling
capacitor, manufacturable in flex panels if desired. These are built on Kapton film, with sputtered copper. Then 0.5 micron of Tantalum is sputtered, and subsequently anodized to produce 1,000 A of Ta2O5. Capacitances are 200nf/cm sq.

Session III had a mixture of wearable computers and smart cards
Hiroyuki Mori of IBM talked of the size reduction of
portable computers, down to the size of the Palm Pilot. It is
a small step to headphones and voice recognition, so that a
computer in a pocket or built into a jacket or a shirt can provide the communication and information for major communications without screen viewing.
Is this computing, or is this smart cellular phone technology ? A little of both. Processors will operate at 340 MHz.Technology is moving rapidly, but it will still be a few years.
Aschenbrenner told of thinner Silicon die - to 10 micron!
This makes them so thin they are flexible, so the resultant chip
on flex assembly can be folded !
Applications include medical records, Airline bag tags for
instant locating, with sensors up to 10 meters away.

Packaging Technology Structures, Session IV
Kimura of Mitsubishi talked of their stacked chips
technology for mobile phone applications. They stack both MCP and SCP packages.
For the MCP stacking, they bond die to the top and bottom of the die paddle, avoiding the connection to the two high chip stack. For the SCP packages, they bump bond the first die, and wirebond the second. An increasingly popular strategy.
Toshiba's work on stacking paper thin chips thins the die
from the initial 15 or more mils to less than 0.13mils, by grinding / honing. A two high stack is placed in a thin package, and the total package height is only 0.55, including lid.
Wire bond is used on rigid substrates, pitch >80 micron
Bump bond is used for rigid flex, pitch 50 micron
Bumpless bonding for flex pitch <10 micron

80 micron is do-able today, 50 micron tomorrow, 50 micron later.
The bumpless direct bonding will take some time to solve
the technology problems. The expectation is that the bonding
will take somewhat high temperature, and bonding pressure, but
no solder or flux.
Suzuki of NGK has been working on a new substrate. They think glass-epoxy is out, there are too many problems with the vias. There is also copper migration along the glass fibers of
the FR4.
Their new substrate is a composite of silica, ceramic and
Epoxy resin. The core is a silica-ceramic / epoxy resin
composite, but the built-up layers are organic + copper. They
claim that laminate technology cannot achieve the wiring density.
The substrates can be punched in the "green" state but can
also have built in vias. They mold the material in the green
state around parallel wires, then cure.
Slices across the wire - ceramic assembly yield an array of
copper conductors suitable for use as vias. In a sense, this is
like the ancient Venetian technique called "millifiore" where
parallel bundles of colored glass fibers were bundled and
sintered to give the desired patterns when sliced across the
stick.

The next Session was on Standardization ( Government Support ) for Electronic Manufacture
Both the talks featured a look ahead for Japan, with the
emphasis on catch-up. The speakers considered Japan to be behind the west by about 5 years ! ( Behind in some things, perhaps, but mostly up-to-date. I think they are exaggerating. ED )

High Frequency and Wireless
Petri Savolainen talked of Smaller, Faster and Cheaper. He indicated that the new target is environmental concerns. Part
of that is red benefit for cellular phones for reduced operating
time per re-charge.

What is the best way forward to reduce size. Stacked
microchips now are the same height ( with die thinning ) and the
same footprint as older single chips, and there are less solder
joints. Substrates are High Density, mostly built-up, with
passive ASICS. Integrated passives are from outside suppliers.
He thinks Japan is ahead on banning lead soldering, and
elimination of other bad processes.
Coming is 24 hour "ON" operation, and "Find Me" roaming -
nationwide or world-wide with one number. The problem is the
station equipment - how will they handle the massive increase in
operating lines ?
The Sharp talk was on the antennas, by Kitaoka. Infrared
transmission is slow, and even the Bluetooth technology at 2.45
GHz will prove inadequate, as well as Microcast at 5.7 GHz.
Instead multichannel data pathways must be found.
That suggests Millimeter Wave technology - OK inside a
house, for example. Goes through walls, and has the bandwidth
for the short house distances. One connection will feed the TVs
in the house, the Computers and the Games.
The antenna is crucial. They mount the antenna on the lid
of the package, and couple to it using electromagnetic couplers.
They have established feasibiity, now they need to optimize.
There is 11db of gain, which means it must be better
someplace and poorer elsewhere. Of course the answer is that
the antenna is not omnidirectional. But you don't need sidewise
gain if the antenna is mounted on the wall of each room, near
the ceiling, and the signal goes mostly out.
Masaharu Itoh of NEC discussed their package for Multilayer low cost ceramic packaging for Millimeter-wave applications. This is co-planar technology for MIMIC applications, and suitable for door openers, car radar, wireless data lines etc. Bandwidth is 60 GHz.
The package is ceramic, with I/O confined to two edges,
peripheral, notched into the ceramic. The feed through to the
side reduces height, which is the more critical dimension for RF
work.
Toshiba also spoke of MIMIC Applications, using BCB for the dielectric. The design used some air bridges for critical leads and to achieve controlled ground plane designs. They prefer Tin-Lead solder with glass ceramic or alumina ceramics, but they do epoxy also. Their air bridges re-deposited on photoresist, which is then dissolved away.

Future of Packaging Technology
Nishamura of Hitachi had the task of looking into the
crystal ball and predicting the future. RHINET is high speed
optical interconnects in an 8X* crossbar switch, parallel
optical with 8.0 Gigabits of information / second. It has a
512kbyte internal memory, for large thruput and low latency.
Input devices can be up to 100 meters away - great for within
building, but this technology is not aimed for outside
buildings.
Optical transmission from the packages is on the edge; 12
channels plus 1 for the clock. Modules can be connected with 12 channel fiber optic ribbon. Hitachi Device Development Center did the LSI chips.
MEMs have had no impact yet in this technology. Because
the manufacture is significantly different, That move will not
be made till the reasons for it are overwhelming.

Takashi Kamijoh of OKI also talked of optical interconnect. He believes we will see interchip free space optical between chips, reducing the density of circuit boards. Free space optical computers are being designed, I/O is the bottleneck with copper wiring, going to optical is necessary.
With optical, 2,000 channels are possible per edge/cm, for
distances up to 40 MM - less than 1/2 inch. This is for
connections within modules. But NO impedance matching is needed. Optical beams go through silicon, so optical connections can be to chips above and below it in a stack.
The output LIDs channel their energies between the die and
a top plate, both of which reflect the signal so that it proceeds along the surface space. Minimum feature sizes need only to be about 1 micron, so we are in the position of doing this.
Output light is through the silicon, with the beam focused
with a silicon Fresnel Lens.

The next session was on environmentally improved Technology - Mostly Lead Free.
Seyama of Fujitsu indicated that Fujitsu has already made the move to Lead-Free solder for their High End computers! The hope is to be lead free for all products by December 2002. All devices by Dec. 2000. Over 50% of Fujitsu PWB technology will be lead free this year also.
Again they are exploring the choices - Tin-Silver, Tin,
Bismuth-Silver, Tin-solder bonds have a reflow soldering
temperature 100 C less than the Sn-Bi-Ag, but Sn-Bi-Ag has
lower TCE stress than Pb-Sn, or even Sn-Ag.
But the molding compound should be environmentally friendly. Masatoshi Iji of NEC discussed progress in getting the Bromine out of semiconductor packaging. Solutions lie in using a new metal hydride compound from Germany, or in increasing the inorganic fillers in the molding compound. They are successfully using up to 90 % fill by weight. Wow - that seems impossibly high, but perhaps if it is stated in volume percent, it might be below the 60% at which matrices fall apart.
But elimination of the brominated salts require self-
extinguishing by other means. Foam layers are being proposed,
with pyrolitic resistant material - so that the fire goes out as
heat is transferred to other parts of the board. Bisphenol and
Novolac Epoxy molding compounds were discussed as usable for the molding compounds.
The remaining element to change is the Printed Wiring
Board,as discussed in the presentation by Happoya of Toshiba. The Libretto and Dynabook notebooks have already moved to non-bromine boards.
In Germany, this is called Blue Angel technology, in Sweden, TCOGY, in Finland, White-Swan. The US is lagging here. The US PCB manufacturers lost the order from Toshiba because they could not deliver bromine-free boards.
The goal is to go Lead-free, Bromine-free, no Antimony, No
chlorine in the photoresist, No styrene foam in the packaging,
all with no reliability penalty !
Flame retardance is by the use of a Nitrogen-Phosphorus
compound in FR-4 grade material.
Green solder resist is green because of Antimony. Antimony-
free resists is blue !
The only penalty, for now, seems to be hole punching, which
is not as good now, but improving.
Jan Vardaman did an Overview of Lead-Free soldering
progress. The world-wide fear is regulation - over regulation
beyond what is necessary. Since Japan is export dependent, they are the first to move to lead free. It is Europe that is the driver for environmentally safer products, not the US. Some US activity is happening - notably H-P, Sun, IBM, CISCO, Nortel, 3com, Motorola, Ford, Delco.
Matsushita is late to this revolution, so they have started
by making their TV products environmentally friendly, and are
moving on other things.

Administrative Matters
This was the end of the fourteen year cycle set up when the
first Japan Workshop was created. All the companies that co-
sponsored have had their turn as General Chair, and we start the
cycle again. Since NTT was first ( with Dr Watanabe of NTT
Atsugi Lab, the next chair will be Tohru Kishimoto. But the
committee wanted involvement by other companies at the General Chair level. They voted to set up two co-chairs for the future next 14 years, using one of the original companies for one chair for their experience and familiarily with the workshop
organizing tasks, and a co-chair from one of the other companies
to be invited: Sony, Casio, Canon, Matsushita, Kyocera, perhaps Sanyo or Ibiden.
The workshop secured good papers, and remains mostly papers from Japan, as it should, with just enough papers from the US and Europe to add input to each session, and to stir the
questions asking activity. Younger Japanese participants are
beginning to ask questions also, so one of the major goals of
this workshop - to promote dialog, is really happening.

JW Balde - 3/12/00
Condensed from
An Interconnection Decision Consulting Report

Note: The next international meeting of the CPMT Systems
Packaging Committee will be Workshop in the last week of
January 2001,in Barcelona, Spain. Reserve the date on your
travel calendar. (editor’s note: to subscribe to IDC’s full notes on many meetings of interest to CPMT members call 1 201 788 5190. We appreciate the occasional condensation made available to CPMT members.)