PackCon 2000 ///
CPMT IEMT Symposium
October 2 - 4, 2000
Santa Clara Convention Center
Santa Clara, California
register on www.semi.org
Monday, October 2
Session 1 ----9:30 - 12:00
Systems Specific Packaging Technologies
Chairs: Achyuta Achari, Visteon - Luu Nguyen, National Semiconductor
The session offers an exciting look at packaging technologies outside mainstream semiconductor packaging. This year's session covers power devices, use of thermoplastics in automotive applications, 3D packaging for hearing aids, packaging for optical devices, and a look at wafer level packages.
Session 2 ----- 9:30 - 12:00
Package and System Modeling
Chairs: Paul Harvey, 3M -- Jon Long, Altera
This session presents papers that describe process-modeling technoiques for manufacturing yield optimization, mechanical modeling techniques for thermo-mechanical reliability improvement and electrical modeling techniques for enhanced electrical performance.
Session 3 ---- 1:30 pm - 5:15 pm
Emerging Trends in Semiconductor Packaging
Chair: Reha Uzsoy, Purdue University
The rapidly increasing complexity, power consumption and level of integration of semiconductor devices is leading to more and more fuctions being integrated on the chip instead of the board level. This creates a need for novel packaging solutions that are functional reliable and cost effective. This session examines a number of such areas, including chip-scale packaging and alternative interconnect technologies.
Session 4 ----1:30 pm - 5:15 pm
Package Reliability
Chairs: Nduka Ekere, University of Salford -- Atila Mertol, LSI Logic
The papers in this session focus on the very important issue of Package Reliability. The eight papers cover a wide range of topics, from wafer level burn-in and test, to the effect of voiding in CSP/BGA solder joints, flux-underfill compatibility and process/reliability analysis of No Flow underfill for flip-chip delamination. The session has a strong international flavor, with a good industry/academic mix.
Tuesday, October 3
Session 5 ---- 8:30 -- 9:30 and 10:30-12:00
Package Assembly
Chairs: Michael Salagoity, Solectron -- Vern Solberg, Tessera
Package Assembly typically covers a wide range of activities focused on efficent and cost effective methods to package devices. This session offers interesting papers that cover a number of topics including novel uses of SMT equipment, rheology of underfills, chemical wafer thinning and use of a wetting balance test.
Session 6 --- 8:30-9:30 and 10:30-12:00
Environmentally Friendly Electronics Manufacturing: Lead-free, Halogen-free, and Solder Alternatives
Chairs: Jan Vardaman, TechSearch -- Eric Jung, FhG-IZM
The environmentally friendly manufacturing movement is being driven by consumer demand. It is a market pull, not a technology push movement. Issues include the development of alternatives to lead-based solders, board and component finishes and bumps for ICs. There are also environmental initiatives to eliminate bromine for plastics/epoxies used in manukfacturing. Halide-free PCBs have already been introduced by several companies. This session addresses many of these environmental issues highlighting the latest developments.
Session 7 ---- 1:30 pm - 5:15 pm
Flip Chip Array Packaging
Chair: Linda Matthew, TechSearch -- Dr. Tim McLaren, Washington State University.
This session has papers which focus on several different technologies for the manufacturing and successful implementation of flip chip devices and packages. The technologies range from polymer bumps to screen printed solder bumps. Issues with large devices and harsh environmental applications are discussed.
Session 8 ---- 1:30 pm - 5:15 pm
Electronics and Semiconductor Manufacturing Optimization
Chairs: James Steele, Medtronics -- Dr. Ismail Fidan, University of Northern Iowa.
With continued intense cost pressures, manufacturers of electronics and semiconductors continue to look to optimization to give them a competitive advantage in the market place. The papers in this session, which have a strong international flavor, address a wide range of topics related to manufacturing optimization with respect to quality, cost and efficiency. The optimization areas addressed are: Surface Mount Technology, Electrical Test, Tool Refurbishment, Remanufacturing and Semiconductor Processing.