SANTA CLARA VALLEY CHAPTER

CPMT CALENDAR FOR FALL 2000
NOTE: All meetings are on 2nd Wednesday evening. Check WEB for changes: www.cpmt.org/scv
WEDNESDAY, SEPTEMBER 13
Subject: PACKAGING TRENDS IN LIGHTWAVE ELECTRONICS
Speaker: Jeff Montgomery (ElectroniCast)
Time: Dinner at 6:30; talk at 7:30 p.m.
Place: Ramada Inn, 1217 Wildwood Ave, Sunnyvale
Cost for dinner: $20 if reserved
RSVP: 1-800-686-9366 or cpmt-ttarter@mindspring.com

Abstract: Telecommunication industry trends are paralleling computer industry trends. Improved communications yield economic payback, supporting continuing technology development. Equipment has advanced from relays to ICs, from copper wire to optical fiber. User demand and economic return support order-of-magnitude performance gain every couple of years, but permit no size increases. From 1975 to 1995, lightwave transport advanced from megabits to gigabits, 1995-2000 advanced to terabits per fiber, by 2005, petabits per fiber cable. Lightwave transmitters and receivers have evolved from board assemblies to complex hybrid optoelectronic ICs (OEICs), complex monolithic ICs in development. Lightwave electronics packaging must accommodate automated assembly and test, maintain micron-level dimensional tolerances and provide excellent heat transfer production levels are reaching millions per vendor.
Jeff Montgomery's Bio:
Jeff Montgomery; BSEE, Illinois Institute of Technology; MBA, University of Santa Clara; Chairman and founder, ElectroniCast Corp. 46 years of professional experience in the electronics industry, as a microwave engineer, marketing manager and CEO. Since 1967, full time in electronic/communication industry forecasting /planning, focused on advanced technology products. Life member of IEEE and member, SPIE and OSA.

OCTOBER 11
Subject: PACKAGING OF RAMBUS RDRAMS
Speaker: Bel Haba (RAMBUS)
Abstract: In the past two decades, the microprocessor speeds have outpaced the memory bus leading to a bottleneck. Now a new technology solves this problem by transferring 16 bit data at speeds as high as 800 MHz while delivering a 1.6 Gbits/s bandwidth. Lately, speed of 1.066 GHz for short channel and 1.6 GHz for QRSL were announced. To achieve this milestone, the electrical, mechanical and thermal characteristics of die packaging became very important. And in this talk we tackle these issues as well as the various packaging technologies that are applicable.
Bel Haba’s Bio:
Belgacem Haba originated in Algeria. MS and PhD in Materials Science and Engineering from Stanford University, California. Manages the packaging development program at Rambus Inc., Tessera three years as a manager of the wafer level packaging and the high density multi-layer substrate activities. Laser researcher at IBM and NEC.

NOVEMBER 8
Subject: MULTIMEDIA EDUCATION MODULES IN ELECTRONICS PACKAGING
Speaker: Paul Wesling (Compaq)
Abstract: MULTIMEDIA EDUCATION MODULES IN ELECTRONICS PACKAGING
Multimedia training is now available on the Internet – from universities and commercial courseware companies provided for a fee, some for free. Some of the technologies used for preparing multimedia educational modules, including freely available authoring packages, a number of modules in the electronics packaging field that can be accessed on the CPMT Society website will be demonstrated. Examples include two virtual packaging laboratories, lectures on thermal design and analysis, and a number of graduate-course lectures. Content is organized topically, based on the Subject Index from the CPMT Transactions, and all technologists are being encouraged to transform their technical talks into short talks suitable for adding to the growing content.

Paul Wesling’s Bio:
Paul B. Wesling (M '68, SM '84) B.S. in electrical engineering
M.S. in Materials Science Stanford University.
Various positions in R&D, reliability, component engineering,
manufacturing engineering, and management at Amdahl Corporation and Compaq Computer (Tandem Division). Since 1985, advanced package development and thermal analysis for multichip modules, and currently develops technical education for the software and hardware R&D groups. CPMT Publications Vice President for 13 years. CPMT Society's webmaster, with a focus on multimedia content for education in packaging.

DECEMBER 13

Subject: IC PACKAGING ROADMAPS
Speaker: Dave Tovar (IPAC)
Abstract: Microminiaturization of microelectronic packages continues to be the leading factor for advanced interconnect technologies . In order to keep up, the major assembly subcontractor houses have found it necessary to combine their research and development efforts either through the integration of internal departments/divisions or else by the establishment of business partnerships/alliances with key customers. In this manner, R&D efforts can proceed in a multiplexed fashion that will result in improved time-to- market of new products and lower prices.
Recent package introductions in the area of advanced interconnects include:
Stacked Die – Two and three memory die stacked on top of each other in a chip scale package (CSP) format.
Metal Lead Package (also known as QFN) – CSP with embedded leadframes, no leads
Flip Chip (FC) – Single or multichip wireless packages intended for high performance or high leadcount packages.
Wafer Scale Integration (WSI) – Fan in designs from tight peripheral bond pad designs to more manageable area array formats through the use of an organic dielectric and a metallic interconnect.
Dave Tovar’s Bio:
BS in Analytical Chemistry MS in Chemical Engineering from SJSU. 25+ year veteran of the semiconductor industry, Engineering and managerial positions in R&D, manufacturing operations including materials, design, process, product engineering, electrical testing, failure analysis, and R&QA at IBM, Fairchild, National Semiconductor, SEEQ, VLSI Technologies, Synergy, ChipPac, PacTech, and IPAC.

WEDNESDAY JANUARY 10, 2001
Subject: Substrate Technology Brings Chip-Like Geometries To Board-Level Dimensions
Speaker: Jack Belani, X-LAM Technologies (K&S)
Abstract: The semiconductor industry has always led in shrinking chip feature geometries compared to the board industry, creating a "gap" that challenged the packaging community to find low cost solutions for connecting the chips to the outside world As the industry enters the sub-quarter micron era and pin-counts on the chip escalate into the 1000s, conventional substrate technologies are unable to bridge these tight geometry devices to the next level of interconnect on the board. A thin film solution that uses wafer fab-like process steps built in a large panel flat-panel display-like equipped high volume facility that leverages conventional board interconnect technologies clearly appears to be what the industry needs. These thin film structures are fabricated on large panels to achieve cost efficiencies onto organic boards that mate in a BGA format to the next level of interconnection.

Jack Belani’s Bio : MS Materials and Metallurgical Engineering, Illinois Institute of Technology, a B.Tech from the Indian Institute of Technology.
Currently President of X-LAM Technologies unit of Kulicke & Soffa Industries. Vice President of Assembly and Packaging at Cypress Semiconductor for 3.5 years, Director of Package Technology at National Semiconductor for 19 years.