Advance Program

THE FIFTH
VLSI PACKAGING
WORKSHOP
OF JAPAN

Sponsored by
The IEEE Components, Packaging, and Manufacturing Technology Society
and
The National Institute for Standards and Technology

December 4 – 6, 2000
Kyoto Kokusai Hotel
Kyoto, Japan
THE FIFTH VLSI PACKAGING WORKSHOP OF JAPAN
December 4 - 6, 1998
Kyoto Kokusai Hotel, Kyoto, Japan

The IEEE CPMT Society and the National Institute for Standards and Technology are jointly sponsoring the Third VLSI Packaging Workshop of Japan to be held in Kyoto. The speed and pin counts of VLSI packages continue to increase. The VLSI packages must be electrically and thermally enhanced to keep up with the VLSI silicon advances. They are also required to be as small as possible, higher in performance and lower in cost to meet system requirements for the multimedia Age. The goal of this Workshop is to accelerate the Interaction? among experts and leaders in various packaging areas of material, components, assembly process, manufacturing equipment and package design for the 21st Century. All attendees are expected to be specialists in the fields.
To encourage a frank exchange on up-to-the-minute findings, and cameras and tape recorders are not permitted. A copy of the Extended Abstracts will be given to Workshop participants. There will be two keynote addresses and 40 presentations in 10 plenary sessions. The workshop will be held in English.

General Chairman: Fuminori Ishitsuka, NTT
Phn:+81-46-222-6125, Fax:+81-46-222-5519,
E-mail: ishi@atsu1.nel.co.jp
Vice Chairman: Atsushi Nakamura, Hitachi
George Harman, NIST
Past Chairman: Nobuo Kamehara, Fujitsu
Japanese Committee:
Kanji Otsuka, Meisei Univ., Hiroshi Shibata, Osaka Inst. of Tech.
Tomoshi Ohde, Sony Yoichi Kohara, Oki
Kenji Kasuga, NEC, Hyung-Woo Lee, Tessera Japan
Toshio Sudo, TOSHIBA, Hisashi Tomimuro, NTT Electro. Tech.
Naoto Ueda, Mitsubishi
US Committee:
Len Schaper, U of Arkansaw, Ephriam Suhir, Lucent Tech.
Jan Vardeman, TechSearch John L. Prince, Univ. of Arizona
Bill Hamburgen, Compac C.. Rao R. Tummla, Georgia Inst. of Tech.
European Committee:
Karel Kurzweil, Bull, France Gerard Nicolas, Leti, France
Herbert Reichl, Tech. Univ. of Berlin, Hans Hentzell, Linkoping Univ.

Asian Committee:
Albert W. Lin, ITRI/ERSO, ROC Jung-Ihl Kim, Anam, Korea
Thiam-Beng Lim, N.Univ.of Singapore, Kyung-Wook Paik, KAIST,Korea

Advance Registration Form
--- THE FIFTH VLSI PACKAGING WORKSHOP OF JAPAN ---

[Print clearly. Please make enlarged copy of this form when using FAX]
(first) (middle) (last)
Name_______________________ _______ ___________________
Affiliation _________________________________________________
Department________________________________________________
Address (office) ____________________________________________
City__________________________ State _______________________
Zip___________________________Country_____________________
Phone +______ ( _____________ ) _________________________
Fax +______ ( _____________ ) _________________________
E-mail ____________________@___________________________
**E-mail address required! We will send the receipt confirmation by email?
** Total amount of payment \ ,000-

** Choose one from the following payment methods
1. I prefer to pay the total amount by Credit card : [ ]
Visa [ ] , Mastercard [ ] , American Express [ ]
Card Number______-______-______-______, Exp. Date ____/____
Authorized Signature________________________,Date __________

2. I sent the total amount by bank to bank transfer : [ ]
Account Name VLSI PACKAGE WORKSHOP
Account Number 4212450
Bank Name Itami branch (#355), Sakura Bank
Remittance date _____________,
Bank Name ___________________

Hotel Reservation Form
--- THE FIFTH VLSI PACKAGING WORKSHOP OF JAPAN ---

[Print clearly. Please make enlarged copy of this form when using FAX]
(first) (middle) (last)
Name ____________________ ______ ______________________
Affiliation _________________________________________________
Department________________________________________________
Address (office) ____________________________________________
City _________________________State ________________________
Zip__________________________Country ______________________
Phone +______ ( _____________ ) _________________________
Fax +______ ( _____________ ) _________________________
E-mail ____________________@____________________________

I want to reserve _____ room(s) of
Kyoto Kokusai Hotel [ ] Sanjo-Karasuma Hotel [ ]
Workshop Hotel 10 min. walk
from Dec. _______ ( ____ nights ) for _________ people(s)
The rate for one night with breakfast including tax :
Kyoto Kokusai Hotel Sanjo-Karasuma Hotel
Single [tiny room] \11,500.- \ 9,000.-
Double/twin (for One people) \13,000.- \11,500.-
Double/twin (for Two people) \20,000.- \16,000.-

Special requirements : _____________________________________

** Total amount of payment \ , 00-

The payment will be made at a hotel. Major international credit cards are acceptable. The Hotel will hold the rooms for the Workshop until Nov. 8.
You are encouraged to send this form by mail or FAX to the following address before Nov. 8, 1996.
Mr. Akihisa Katayama
Kyoto branch, Kinki Nippon Tourist Co., Ltd.
Shijo-Karasuma, Shimogyo-ku, Kyoto 600, JAPAN
Phone : +81-75-221-7401, Fax: +81-75-223-5192

Advanced Program

***Monday, Dec. 4 th ****************

10:00-12:00 Welcome & Invited Talks
Chair ?
1. Opening Remarks F.Ishitsuka, NTT

2. Multi-Gb/s CMOS LSI Design and Requirements for LSI
Packages, Y.Ohtomo, M.Nogawa, Y.Kitamura, NTT

3. High-Performance 80nm Gate Length SOI-CMOS Logic Technology with Full Level Dual Damascene Cu /Very Low-k Interconnects, M. Yamada, Fujitsu Ltd.

4. H. J. Liaw, RAMBUS
*******************************
12:00-13:00 Lunch
**********************************
13:00-15:00 Session 1 3-D Packages
Co-Chairs:H.W.Lee
1.1. Three Dimensional Stacked Module Structure
T. Sato, N. Tanaka, K. Takahashi, ASET
1.2. Novel High-Volume Manufacturing Technology for 3D IC
Packages,
J. Reche, P. Halahan, R. Korczynsky, Tru-Si Technologies
1.3 The Same Die Stack CSP Packages:Enabling Flexibility in Chip
Stacking, Flynn Carlson, ChipPAC, Inc.
1.4. Tessera Stacked Die CSP Technology
M. Warner, Tessera
**************************************************
15:00-15:30 Coffee Break
********************************************
15:30-17:30 Session 2 Electrical Performance
Co-Chairs: T. Sudo and L. Schaper
2.1. Measurement Evidence of Mirror Potential Traveling on Transmission Lines, K. Otsuka, T. Usami*, Y. Ohdate*,and Y. Ikemoto** ,Meisei Univ., *Univ. of Tokyo, ** Fujitsu
2.2. Measurement Study for Lower Impedance Transmission Lines
by the 50 Ohm Set-up and Consequent Performance
Comparison between SPL and MSL with High Accuracy
Y. Ikemoto, T. Usami*, K. Otsuka* , Fujitsu ,*Meisei Univ.
2.3. Power Supply for High-speed Signal,
Y. Odate, T. Usami, K. Otsuka*, T. Suga,
Univ. of Tokyo , *Meisei Univ.
2.4 Signal Transmission in Multi-chip Module Ball Grid Array,
C.P.Hung, C.C.Tu, J.S.Hsieh and J.J.Lee, ASE,Taiwan

***Tuesday, Dec. 5 th******************************

8:50-10:20 Session 3 Process/Materials
Co-Chairs: Y. Hirata and J. Prince
3.1. Studies on Wettability between Solder Bump and Substrate Finishes for Reflowable Underfill Application, T. Wang, C. Lum, P. Miao, T. H. Chew , L. Foo, Questech Solutions Pte Ltd.
3.2. BCB Polymer Dielectrics for Electronic Packaging and Build-up Board Applications, K. Ohba, M. .Kohno, J. H. Im*, P.. Garrou*, T..Komiyatani**,
Dow Chemical Japan, *Dow Chemical USA, **Sumitomo Bakelite Co., Ltd.
3.3. Combination Technology of Low Warpage Epoxy Resin and Vacuum Printing Encapsulation Systems (VPES) for Stacked IC, A. Okuno, N.Ohyama, Y. Ogisu, Japan REC Co.
****************************************
10:20-10:30 Short break
******************************************
10:30-12:30 Session 4 CSP/New package structure
Co- Chairs: H. Kasuga and E. J. Vardaman
4.1. Copper Bump Bonding Technologies on 3D Stacked Devices
Y. Tomita, M. Tago, Y. Nemoto, K. Takahashi, ASET
4.2. New CSP Using the Reversible Interconnection Concept
M. Onodera and T. Suga, Univ. of Tokyo
4.3. Development of TBGA-?Package: High Power Package with Active Ground Plane, Young Heo, ChipPAC, Inc.
4.4. Reliability of the S3-Diepack WLP
J. Simon, TU of Berlin & Fraunhofer IZM
*******************************************
12:30-13:30 Lunch
*******************************************
13:30-15:00 Session 5 Fine-pitch Interconnection(1)
Co-Chairs: Y. Kohara
5.1. Trends in Flip Chip Packaging: The Ultimate Wafer Level
Package, E. J. Vardaman, TechSearch International
5.2. Room Temperature Interconnection of Electroplated Au Microbump by means of Surface Activated Bonding Method
Y. Matsuzawa, T. Itoh and T. Suga, Univ. of Tokyo
5.3. Evaluation of Solder Joint reliability of DCA Assembly by Temperature Cyclic Test, Bending Test, Shear Test and Drop Test? P.J.Zheng, S.H.Ho, C.W.Lee, H.J.Kung, J.Z.Lee, J.D.Wu and J.G. Hwang, ASE, Taiwan
*************************************
15:00-15:30 Coffee Break
***************************************
15:30-17:00 Session 6 Thermal /Mechanical Characterization
Co-Chairs: T. Ohde
6.1. Characterization of Mechanical Failure Mechanisms in Small Area Array IC Package, T. Gregorich, T. Marburger and M. Velez, Qualcomm
6.2. Thermal Characterization of Stacked-Die BGA,
L.W.Lee, J.G.Hwang, H.N.Chen, and J.T.Wu, ASE, Taiwan
6.3. The Relationship between Substrate Components and Thermal
Performance /Stress Issues of Chip Scale Packages, T-C. Huang,
L-W.Lee, C-C. Lee D-P. Lai, and J.G.Hwang, ASE, Taiwan
6.4. Board Level Thermal Simulation System for LSI Packages
N.Yoneda, M. Kitano, H.Miura, I.Shimizu and N.Koike, Hitachi,
*******************************************
17:00-17:30 Coffee Break
*******************************************
17:30-19:00 Panel Discussion
Chairs: A. Nakamura
R. R. Tummala, L. Schaper, Intel and Rambus, A. Nakamura

*********Wednesday, Dec. 6 th*********************

8:50-10:20 Session 7 Modules and Optical Applications
Co-Chairs: H. Shibata and ?
7.1. High-density 3D Packaging Terchnology for CCD Micro-camera System Module,
H. Yamada, T. Togasaki, M. Kimura, H. Sudo, Toshiba Corp.
7.2. System in Package using Chip Stacking Technology
Y. Uchida, Y.Saeki, T.Oka, Oki
7.3. Electrical Interconnection Techniques for 40-Gb/s Optical
Receiver Module, N. Iwasaki, M. Yanagibashi, H. Tsunetsugu,
F.Ishitsuka and M. Hosoya, NTT
*****************************************
10:20-10:30 Short break
******************************************
10:30-12:00 Session 8 Fine-pitch Interconnection (2)
8.1. Material, Problems, Solutions for Wire Bonding to Advanced Copper Low-K Integrated Circuits, G.G.Harman, NIST.
8.2. Ultrasonic Flip-chip Bonding Technology using Preformed UnderfilI Resin, T.Iwasaki, I S.Yamada, M.Kimura, Y.Hatanaka, H.Fujioka, N.Ueda , Mitsubishi
8.3 Room Temperature Direct Bonding of CMP-Cu Film
A.Shigetou, N. Hosoda, T. Itoh, T. Suga, Univ. of Tokyo
***********************************************************
12:00 Closing Remarks
==================================================
Registration Fee
Before Nov. 8, 1996 (received date basis)
* IEEE members, speakers or session chairs \ 43,000.-
*Non-members \ 48,000.-
After Nov. 9, 1996
* IEEE members, speakers or session chairs \ 53,000.-
* Non-members \ 53,000.-
The fee covers refreshment breaks, two luncheons, evening party at first night, walk out lunch on the second day and a copy of the Extended Abstract. Does not include hotel accommodation and transportation from/to Kyoto Kokusai Hotel.

Payment
Payment of the Conference fees should be made in Japanese Yen for the total amount due in one of the following methods:
1) by Credit Card:
Both VISA and Master cards are acceptable. Make sure the expire date of your card and fill in the attached Registration form with your authorized signature. Please print your name, card number, and expire date clearly in the form.
2) by Bank to Bank Transfer:
Make remittance to the following account without any charge for the receiver. Remittance information to identify the sender is required.:
? Account Name VLSI PACKAGING WORKSHOP
? Account Number 4212450
? Bank Name Itami branch (#355), Sakura Bank
Address: 2-3-5 Naka-machi, Atsugi-shi, Kanagawa 243, JAPAN ?
(Tel: +81-462-24-3731, Fax: +81-423-24-5978)
3) by Cash Onsite: (Not applicable for Advance Registration rate)
Only effective for attendee who can use neither method #1 nor #2. Please send the registration form by FAX in advance.
Refund will be made for cancellations received before November 23, 1996. Confirmation for receiving your registration will be sent by E-mail. Receipt will be provided at the Workshop Registration Desk in the hotel lobby.
Accommodation
Kyoto Kokusai Hotel (International Hotel Kyoto), is the headquarters hotel for the Workshop and all Workshop sessions will be held there. You can also choose Sanjo-Karasuma Hotel (10 min. walk distance from the Kokusai Hotel). A block of rooms at special rates has been reserved at both hotels for participants and attendees. Room reservations should be made with the travel agency at Phone : +81-75-221-7401 or Fax : +81-75-223-5192. Reservation must be made by Nov. 8, 1996 to guarantee the rate. After this time reservation will be accepted on a space available basis only.

Location and Transportation
The Kyoto Kokusai Hotel is located in front of the Nijo Castle (Nijo-jo) which is located in the central area in Kyoto and takes 10 minutes by taxi (approximately \1200 fare) from JR Kyoto station The buses are also available from JR Kyoto station. Access to Kyoto is 90 min. by express railway "Haruka" from Kansai Int'l Airport. Access from Tokyo station is about 3 hours trip by using JR Tokaido express line. Add one hour from Narita Int'l Airport.

SEMICON JAPAN?
The largest semiconductor manufacturing related equipments exhibition, "SEMICON JAPAN", will be held in Makuhari (Tokyo area) on 6 - 8, Dec. 2000. Workshop attendees can go to Tokyo after the program and attend SEMICON.

Nijo Castle
The Nijo Castle was originally built in 1603 to be the official Kyoto residence of the first "Tokugawa Shogun", and it was completed in 1626 by the third Shogun. The Ninomaru Palace is a National Treasure which was almost constructed by Hinoki wood and The Ninomaru Garden is famous for its traditional Japanese garden.