Santa Clara Chapter Upcoming meetings

DECEMBER 13

Subject: IC PACKAGING ROADMAPS
Speaker: Dave Tovar (IPAC)
Abstract: Microminiaturization of microelectronic packages continues to be the leading factor for advanced interconnect technologies . In order to keep up, the major assembly subcontractor houses have found it necessary to combine their research and development efforts either through the integration of internal departments/divisions or else by the establishment of business partnerships/alliances with key customers. In this manner, R&D efforts can proceed in a multiplexed fashion that will result in improved time-to- market of new products and lower prices.
Recent package introductions in the area of advanced interconnects include:
Stacked Die – Two and three memory die stacked on top of each other in a chip scale package (CSP) format.
Metal Lead Package (also known as QFN) – CSP with embedded leadframes, no leads
Flip Chip (FC) – Single or multichip wireless packages intended for high performance or high leadcount packages.
Wafer Scale Integration (WSI) – Fan in designs from tight peripheral bond pad designs to more manageable area array formats through the use of an organic dielectric and a metallic interconnect.
Dave Tovar’s Bio:
BS in Analytical Chemistry MS in Chemical Engineering from SJSU. 25+ year veteran of the semiconductor industry, Engineering and managerial positions in R&D, manufacturing operations including materials, design, process, product engineering, electrical testing, failure analysis, and R&QA at IBM, Fairchild, National Semiconductor, SEEQ, VLSI Technologies, Synergy, ChipPac, PacTech, and IPAC.

WEDNESDAY JANUARY 10, 2001
Subject: Substrate Technology Brings Chip-Like Geometries To Board-Level Dimensions
Speaker: Jack Belani, X-LAM Technologies (K&S)
Abstract: The semiconductor industry has always led in shrinking chip feature geometries compared to the board industry, creating a "gap" that challenged the packaging community to find low cost solutions for connecting the chips to the outside world As the industry enters the sub-quarter micron era and pin-counts on the chip escalate into the 1000s, conventional substrate technologies are unable to bridge these tight geometry devices to the next level of interconnect on the board. A thin film solution that uses wafer fab-like process steps built in a large panel flat-panel display-like equipped high volume facility that leverages conventional board interconnect technologies clearly appears to be what the industry needs. These thin film structures are fabricated on large panels to achieve cost efficiencies onto organic boards that mate in a BGA format to the next level of interconnection.

Jack Belani’s Bio : MS Materials and Metallurgical Engineering, Illinois Institute of Technology, a B.Tech from the Indian Institute of Technology.
Currently President of X-LAM Technologies unit of Kulicke & Soffa Industries. Vice President of Assembly and Packaging at Cypress Semiconductor for 3.5 years, Director of Package Technology at National Semiconductor for 19 years.