51st ECTC Program
Sessions
Wednesday, 30 May 2001
8:00 A.M. - 12:00 P.M.
Session 01: High Speed Packaging
Committee: Optoelectronics
Session CoChairs:
Werner Hunziker – Opto Speed SA
Tel: 011-41-16332172
Fax: 011-41-16332158
Email: whunziker@optospeed.ch
Jean Trewhella
IBM Research
Tel: 914-945-2786 Fax: 914-945-1974
Email: jeanmh@us.ibm.com
**Improved VCSEL structures for 10 Gigabit-Ethernet and next generation
optical-integrated PC-boards
F. Mederer, R. Jager, J. Joos, M. Kicherer, R. Michalzik, M. Reidl,
H. Unold, A.Cheleg, K.J. Ebeling, S. Lehmacher, B.
Wittmann, and A. Neyer – University of Ulm
**Highly Alignment Tolerant InGaAs Inverted MSM Photodetector
Heterogeneously Integrated on a Differential Si CMOS Receiver
Operating at 1 Gbps
Michael Vrazel, Jae Joon Chang, In-Dal Song, KeeShik Chung, Nan
Marie Jokerst, Martin Brooke, April Brown and
D. Scott Wills – Geogia Institute of Technology
**3.125 Gbps/channel 4-channel Parallel Optical Transmitter and
Receiver Module with MT-RJ Receptacle
I. Yoneda, K. Yamauchi, S. Yunoki, K. Matsumoto, T. Nakamura,
K. Miyoshi and N. Nagahori – NEC Corporation
**Towards 10 Gbps/channel in Parallel Optical Link
Ingo Schmale – Infineon Technologies
**Low Cost CWDM Optical Transceivers
Eric B. Grann – Blaze Network Products
**Short Wave SFF Small Form Factor Transceiver
S. Abe, K. Tobita, T. Shinozaki, K. Arai, K. Takeshita, K. Tanaka
and Y. Isono –Fujikura Ltd.
Session 02: Wafer Level and Chip-Scale
Packaging
Committee: Advanced Packaging
Session CoChairs:
Tim Adams – Dow Corning Corporation
Tel: 517-496-8867 Fax: 517-496-5121
Email: tim.adams@dowcorning.com
Jeffrey A. Knight – IBM Corporation
Tel: 607-757-1015 Fax: 607-757-1860
Email: knightj@us.ibm.com
**Encapsulated Double-Bump Wafer Level: Design and Reliability
Beth Keser, Treliant Fang, Dianne Mitchell, Betty Yeung, Charles
Zhang, and Jerry White – Motorola
**Development of Low-cost and Highly Reliable Wafer Process Package
Atsushi Kazama, Toshiya Satoh, Yoshihide Yamaguchi, Ichiro Anjoh,
Asao Nishimura – Mechanical Engineering
Research Lab. – Hitachi, Ltd.
**A Complete Solution for the Design and Manufacturing of High-Reliable,
Non-Leaded CSPs like QFN
Gerd Kuehnlein, Arnold Bos – ESEC SA
**Wide Area Vertical Expansion (WAVE) Package Design for High
Speed Device Application: Performance and
Reliability
Y.G. Kim, I. Mohammed, and B.S. Seol –Tessera Inc.
**Development of Low Cost, Highly Reliable CSP Using Gold-Gold
Interconnection Technology
S. Isozaki, T. Kimura, T. Shimada and H. Nakajima – NEC Corporation
**A Novel Low-Cost Pluggable Chip Scale Package for High Pin-Count
Applications
Andreas Cangellaris, Jose Schutt-Aien, Ton Wang, Charlie Ogata,
James Jeon, S.W.Crane, Jr. – University of Illinois at
Urbana-Champaign
Session 03: Reliability Test Methods
Committee: Quality & Reliability
Session CoChairs:
Donna Noctor
Lucent Technologies
Tel: 610-391-3545 Fax: 610-391-3050
Email: dmnoctor@lucent.com
George Harman – NIST
Tel: 301-975-2097 Fax: 301-948-4081
Email: george.harman@nist.gov
**Moisture Blocking Planes and Their Effect on Reflow Performance
in Achieving Reliable Pb-Free Assembly
Capability for PBGAs
R. L. Shook, D. L. Gerlach, B. T. Vacarro – Lucent Technologies
**Whole Field Displacement Measurement Technique Using Speckle
Interferometry
K.J. Cote and M.S. Dadkhah – Conexant Systems
**Scope and Limitations of Current Acoustic Microscopy Techniques
for Emerging High Density Packages
S. Canumalla, P. Viswanadham –Nokia Mobile Phones, Inc.
**An Accelerated Reliability Test Method to Predict Thermal Grease
Pump-Out in Flip Chip Applications
Chia-Pin Chiu, Biju Chandran, Mike Mello, Ken Kelley – Intel
Corporation
**Mechanism and Growth Rate of Underfill Delaminations in Flip
Chips
S. Jakschik, F. Feustel and E. Meusel – TU Dresden, IHM
**Impact of JEDEC Test Conditions on New-Generation Package Reliability
Lei L. Mercado, Vijay Sarihan and Brian Chavez – Motorola
Inc.
.
Session 04: Package/Board Design
Committee: Modeling & Simulation
Session CoChairs:
John L. Prince
Univ of Arizona
Tel: 520-621-6187 Fax: 520-621-2999
Email: prince@ece.arizona.edu
Andreas Cangellaris
University of Ilinois at Urbana
Tel: 217-333-6037 Fax: 217-333-5962
Email: cangella@staff.uiuc.edu
**Optimizing the Package Design with Electrical Modeling and Simulation
Quan Qi, David Quint, Mark Frank, Tim Michalka, and Karl Bois–
Hewlett Packard Company
**Package Capacitors Impact on Microprocessor Maximum Operating
Frequency
A. Waizman and Chee-Yee Chung – Intel Corporation
**Design and Packaging Challenges for On-board Cache Subsystems
Using Source Synchronous 400 Mb/s Interfaces
Nam Pham and Moises Cases – IBM Corporation
**Microwave Frequency Model of Wafer Level Package and Increased
Loading Effect on Rambus Memory Module
J. Lee, B. Choi, S. Ahn, W. Ryu, J.M. Kim, K.S. Choi, J.K. Hong,
H.S. Chun and J. Kim – KAIST
**Over GHz Low-Power RF Clock Distribution for a Multiprocessor
Digital System
W. Ryu, A.L.C. Wai, F. Wei, W.L. Lai and J. Kim – KAIST
**Modelling and Characteristics of the Polymer Stud Grid Array
(PSGA) Package: A Complete Qualification
A. Chandrasekar,B. Vandevelde, E. Driessens, P. Pieters, E. Beyne,
W. De Raedt and B. Nauwelaers – IMEC vzw
There are 38 Sessions, they are given 4 in parallel. To see the complete list of papers use the web site