Final Program
Future Directions
in IC and Package Design Workshop (FDIP)
sponsored by: CPMT
Components, Packaging, and Manufacturing
Technology Society of the IEEE
organized by:
CPMT Technical Committee on Electrical Design, Modeling, and Simulation
(TC-12)
October 27, 2001
Royal Sonesta Hotel
Cambridge, Massachusetts
The goal of this new workshop is to provide a forum to address the future needs associated with the design of next generation ICs and packages. The Technical Program Committee solicited invited presentations from experts in the university and industrial communities. The workshop is held in conjunction with the 10th IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 2001) in order to enhance this conference with presentations that give directions for future requirements and developments in the area of electrical analysis and design. The workshop will foster active participation and discussions from all the speakers and attendees during the meeting.
Workshop Chairs:
Alina Deutsch Madhavan Swaminathan
IBM Watson Research Center Georgia Institute of Technology
Technical Program Committee:
Ronald Bracken - SRC Mahadevan Iyer - IME, Singapore
Andreas Cangellaris - University of Illinois George Katopis
- IBM Poughkeepsie
Moises Cases - IBM Austin Istvan Novak - SUN
Chi-Shih Chang - X-LAM Technologies Toshio Sudo - Toshiba, Japan
Paul Franzon - North Carolina State University Gregory Taylor
- Intel Oregon
Hartmut Grabinski - University of Hanover, Germany Lewis Terman
- IBM Watson Research
Harold Hosack - Semiconductor Res. Corp. Ryszard Vogel - Nokia,
Finland
Program
11:00 am - 1:30 pm Registration for workshop and EPEP in Charles
B Room
1:15 - 1:30 pm Welcome Remarks, Madhavan Swaminathan, GIT, Alina
Deutsch, IBM
SESSION I: SYSTEM DESIGN
1:15 - 3:00 pm
Session Chair: Chi-Shih Chang, Kulicke & Soffa
1. Next Generation System Design Challenges and Opportunities
Derek Tsai, SUN Microsystems
2. System and Package Design Using the Low-Power Transmeta Processor
Robert Montoye, IBM
3. Optimization of Electrical Package Design and PCB Design for
CSP Age
Atsushi Nakamua, Hitachi, Japan
3:00 - 3:45 pm - Refreshment Break
SESSION II: TECHNOLOGY AND TOOLS
3:45 - 5:30 pm
Session Chair: Harold Hosack, Semiconductor Research Corporation
4. Integration of RF Elements and Passives for Telecommunication
Paul Collander, P. Laukkala, R. Vogel, Nokia Networks, Finland
5. Optical Interconnections Inside the Processor Box
Lewis Terman, IBM Watson Research Center
6. Fast Solvers and "Full Problem Analysis", the Remaining
Challenges
Jacob White, MIT
5:15 - 5:30 pm Closing Remarks, Madhavan Swaminathan, GIT, Alina
Deutsch, IBM
Workshop will be held at the Royal Sonesta Hotel. The address is 5 Cambridge Parkway, Cambridge, Massachusetts 02142-1299, phone: (617) 491-3600, fax: (617) 661-5956. The hotel is holding a block of rooms for participants at a special rate of $125 and the rest at $195 plus 4% city tax and 2.75% CCF tax. Reservations must be made by calling the hotel directly by October 7, 2001 to receive these rates.
Additional information may be obtained from the workshop chairs:
Alina Deutsch Madhavan Swaminathan
deutsch@ieee.org madhavan.swaminathan@ece.gatech.edu
phone: (914) 945-2858 phone: (404) 894-3340
fax: (914) 945-2141 fax: (404) 894-9959
and the workshop administration:
Paul Baltes
epd@engr.arizona.edu
phone: (520) 621-3054
fax: (520) 621-1443
Updates will be posted at the workshop web site at: http://www.cpmt.org/conf/fdip01/fdip.html
and http://www.epep.org. The workshop is open to all attendees
of the IEEE Topical Meeting on Electrical Performance of Electronic
Packaging. Attendees interested in only the workshop will be
charged a $50.0 fee which will cover refreshments and digest of
abstracts. All attendees must register by September 28, 2001
by sending email to epd@engr.arizona.edu in order to assure adequate
services. On-site registrants will be admitted depending on availability
of seating. Please indicate if planning to attend EPEP'2001.