ECTC Plenary Session

On Wednesday night May 30, Vice President Phil Garrou introduced the Plenary session of ECTC. What unfolded was a exciting discussion of the trade-offs in packaging a fast, hot microprocessor; a projection of the integration of passives, and a perspective of mobile computing from Japan.

V. K. Nagesh of Intel described the challenge to the Package Engineer of the Pentium 4 processor. First he described the chip: a network burst architecture with 20 stages of pipeline and a 400 MHz system bus. It is being built in 0.18 micron at first but then scaling down to 0.13 micron. There are 42 million transistors serving up 598 MIPS. In one of its versions it represents 60W with a peak power density of 130W/cm2. Their desire was to keep the peak junction temperature below 90C, to avoid electromigration. It needed new packaging approaches to accommodate the speed and heat.

Flip chip solder bumps with 225 micron pitch were used, the 4200 bumps were on organic. This evolved from the previous generations where organic was used under the land pad regions. An underfill was used.
They used capacitors on the package as well as on the die side.
It was necessary to lower the chip to heat sink thermal resistance and to use a heat spreader.
They transformed from pin grid array to flip chip PGA

Some of the biggest hurdles that appeared was a dynamic warpage that was only conquered with many variations of materials and processes. The thermal coupling between the chip and the spreader was looked at in detail.
Lessons relearned: Spread heat as soon as possible. With the Pentium III Intel could allow the customer to make the chip contact themselves. However, the Pentium 4 is not your Father's microprocessor so Intel controls this interface very exactly. The trend is to try to reduce the junction temperatures.

John Galvani of AVX had accepted the challenge of "giving a crystal ball on passives" during a weak moment. The crystal ball is cloudy because of the major restructure of OEM to EMS. In addition, in the passives industry the Internet has enabled many business operations that geography used to preclude. Passive uses have discovered using the Internet that they can better manage their supply chain and save up to 40%. On the downside the improvements in design and test software have not progressed as fast as needed by the passive industry.
His comments on board assembly:
1. More uniformity in parts are needed
2. the EMS and OEM expect board suppliers to do R&D at no cost to them.
3. There is a drive to reduce the use of Lead and Bromine in the boards.
4. We need few chip modules or SOP, but who does this?
5. Eventually EMS will take over the design and building of boards, but until then the signals are mixed.
On single chip packaging:
1. Migration continues from bond wires to flip-chip
2. Switch from ceramic to organic structures.
3. Ever higher pin count.
He mentioned that although about 15% of U.S. suppliers identify as being capable of HDI processing, in fact almost all HDI boards are made in Japan.
Ceramic boards have grown competitive with organics but are used mostly for harsh environments.
For passives John Galvani showed date indicating that passives shrink a standard size every 4 years. Certainly part of this is due to the decrease in transistor voltage supplies the rest to advances in packaging and integration.
Predictions:
1. All discretes becoming more space efficient
2. Integrated Passive Devices will be more acceptable to circuit designers when IPDs can be turned around in days not months.
3. Buried passives are coming...really.
4. Continued passive development is needed to keep signal integrity for the new demanding circuit designs.
5. Design tools desperately needed.