The 6th VLSI PACKAGING WORKSHOP of JAPAN
Sponsored by the IEEE CPMT Society and National Institute for Standards and Technology
The VLSI Packaging Workshop of Japan held every second year since 1992 in the ancient capital of Kyoto has become a well-known international workshop of advanced packaging technologies. To monitor the latest trend and focus on the future target, the committee strongly urges you to attend this workshop and participate in the discussion. Bring your latest research results and exchange your opinion with internationally acclaimed experts from industry and academia. Beside engineers involved with packaging, wafer processing experts and circuit designers are cordially invited to bring their breakthrough ideas to solve the current problems of SiP and SoC. Emerging technologies and latest designs in the following areas are of interest to the participants.
| Advanced Fine Pitch Packaging | Wafer Level Packaging |
| 3D Packaging & Chip-on-Chip (COC) | Manufacturing Technology |
| Micro Bumping Technology | Pb Free Interconnections |
| Laminated Materials & Processing | Materials for High Speed Application & Wafer Process |
| RF Components & Modules | Integrated Passives |
| Packaging for Optoelectronics | MEMS Packaging Technologies |
| Failure Mechanisms & Reliability Improvement | Cu Chip Assembly and Packaging Challenges |
| Electrical Performance & Thermal Management |
The workshop will be held in English and each oral presentation will be allowed 30 minutes including 10 minutes for discussion. Authors who give outstanding papers will receive official recommendations for paper submission to IEEE Transactions on CPMT by the Japan Chapter and the Workshop Committee. This workshop will be held at a new location (new KRP facility), and the commercial booths for demonstrating products are available adjacent to the workshop hall.
Submission of abstracts:
Those who wish to contribute to the workshop should send a two page extended summary* of their paper (including figures) to the Program Chair by June 3, 2002. The title of the paper as well as the names and affiliations of all authors must be appeared on the summary. If the paper is accepted, the summary shall be written to fit in a four-page format for the workshop’s proceedings by September 2, 2002. Notification of acceptance will be given by July 1, 2002. Please consult our website; http://homepage1.nifty.com/ieeetokyo/chapter/cpmt/vlsip.html for more detailed information on the format, the location and the facilities. We are looking forward to your participation. [*: Preferable to follow the format]
Program Chair:
Tomoshi Ohde, Sony Semiconductor Kyushu Corp.
3319-2, Owara, Kunisaki-machi, Higashikunisaki-gun,
Oita-PRF, 873-0511, Japan
Email: Tomoshi.Ohde@jp.sony.com
Phone: +81-978-72-5160, Fax: +81-978-72-5086
General Chair:
Atsushi Nakamura, Hitachi, Ltd.
Email: nakamura-atsushi4@sic.hitachi.co.jp
Vice Chair:
Masahiko Kohno, Dow Chemical Japan
George Harman, NIST
Japanese committee:
Kanji Otsuka, Meisei Univ.
Toshio Sudo, Toshiba
Nobuo Kamehara, Fujitsu
Fuminori Ishitsuka, NTT Electronics
Noboru Iwasaki, NTT Electronics
Michitaka Kimura, Mitsubishi
Tadaaki Mimura, Matsushita
Yasufumi Uchida, Oki
Hyung-Woo Lee, Tessera Japan
Kimihiro Yamanaka, IBM
Hisashi Tomimuro, NTT Electronics
Hiroshi Shibata, Osaka Inst. Tech.
Hisao Kasuga, NEC
Kunihiko Nishi, Hitachi
US committee:
John W. Balde, IDC
Phillip Garrou, Dow Chemical
Sheng Liu, Wayne State Univ.
Len Schaper, Univ. of Arkansas
Ephraim Suhir, IOLON
E. Jan Vardaman, TechSearch
European committee:
Rolf Aschenbrenner, IZM
David Whalley, Loughborough University UK
Soeren Noerlyng, Micronsult, Denmark
Asian committee:
Jung-Ihl Kim, Amkor, Korea
Kyung-Wook Paik, KAIST, Korea
Ricky Lee, HKUST, Hong Kong
C. P. Hung, ASE, Taiwan
Thiam-Beng Lim, IME, Singapore
IEEE CPMT Japan Chapter:
Nobuo Iwase, Toshiba
Hajime Sakamoto, Ibiden