Program Announcement
Future Directions in IC and Package Design Workshop
sponsored by: Your CPMT Society

organized by:
CPMT Technical Committee on Electrical Design, Modeling, and Simulation (TC-12)
October 19, 2002
Hyatt Regency Monterey, Monterey, California

The goal of this workshop is to provide a forum to address the future needs associated with the design of next generation ICs and packages. The Technical Program Committee solicited invited presentations from experts in the university and industrial communities. The workshop will be held in conjunction with the 11th IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEP 2002) in order to enhance this conference with presentations that give directions for future requirements and developments in the area of electrical analysis and design. The workshop will foster active participation and discussions from all the speakers and attendees during the meeting.

Workshop Chairs:
Alina Deutsch Madhavan Swaminathan
IBM Watson Research Center Georgia Institute of Technology

Technical Program Committee:
Tawfik Arabi - Intel Oregon Mahadevan Iyer - IME, Singapore
Andreas Cangellaris - University of Illinois George Katopis - IBM Poughkeepsie
Moises Cases - IBM Austin Istvan Novak - SUN Microsystems
Chi-Shih Chang - Kulicke & Soffa Toshio Sudo - Toshiba, Japan
Paul Franzon - North Carolina State University Gregory Taylor - Intel Oregon
Hartmut Grabinski - University of Hanover, Germany John Prince - University of Arizona
Harold Hosack - Semiconductor Res. Corp. Ryszard Vogel - Nokia, Finland
Lewis Terman - IBM Watson Research

Workshop will be held at the Hyatt Regency Monterey in Monterey, California. The address is One Old Golf Course Road, Monterey, California 93940. The hotel is holding a special block of guest rooms for meeting participants at the very special rate of $145 plus tax, single or double occupancy. Participants are encouraged to register early to insure availability of these rooms. Reservations may be made by calling Hyatt Worldwide Reservations at 1-800-233-1234 or by contacting the hotel directly at 831-372-1234. Be sure to mention that you are attending the EPEP '02 meeting in order to secure the special room rate. Additional information may be obtained from the workshop chairs: Alina Deutsch, deutsch@ieee.org and Madhavan Swaminathan, madhavan.swaminathan@ee.gatech.edu, and the workshop administration, Paul Baltes, epd@engr.arizona.edu. Attendees interested in the workshop will be charged a $60.0 fee that will cover afternoon refreshments, digest of abstracts, and posting of the foils on the CPMT Society TC-12 web site. All attendees must register by September 13, 2002 using the EPEP'02 website at www.epep.org in order to assure that the workshop is being held. On-site registrants will be admitted depending on availability of seating.

The following talks are planned:

Future Directions for Intel Microprocessors and Packaging, Zane Ball, Intel Corporation
Network Processors, Nevin Heintze, Agere Systems
Optimization of Electrical Package Design and PCB Design for the CSP Age, Atsushi Nakamura, Hitachi, Ltd.
The Impact of Chip and Package Design on Radiated EMI, Todd Hubing, University of Missouri-Rolla
Research on Full-Chip Analysis, Chung-Kuan Cheng, University of California, San Diego
Nanotechnology for the Information Age, Hans Coufal, IBM Corporation