2002 TC-14 Spring Workshop
of the IEEE Systems Packaging Committee
at Research Triangle Park, May 14-16

Condensed from an Interconnection Decision Consulting Report
by John ( Jack ) Balde

Overview

This Workshop was held for the first time in Research
Triangle Park, North Carolina. We learned form the last
workshop that it is essential to have local companies involved in
a workshop so that they can attend without travel dollars in
these tight financial times. We further learned that if half
of the attendees did not travel and stay in the Hotel, we needed
to arrange for minimal registration fees and a hotel that had
low rates for those who did travel to the meeting.

Attendance was 48, an increase over the 38 of
Scottsdale, except that breakeven for the workshop was only 45 so
the meeting was financially successful. The workshop itself was
very successful.

The plan was to have two optical interconnect sessions,
one on the planar interconnect of the first level of Photonics.
Another session was to be medical packaging, with the others
Electrical performance and modeling and Applications.

A successful plan as far as the optical session went, and
the Electrical and Applications were OK. The problem was in the
medical session. It proved to be fairly easy to get early
committment for papers, but then just before the workshop people
started to drop out.

The reason seems to be that medical Developments are
usually presented at medical conferences, focusing on the
concepts of the new technology with minimal interest in the
packaging. Given a choice, speakers would rather present for
the concepts rather than the what they perceive to be the
details

A useful lesson if we try for medical packaging sessions
in the future.

Keynote Presentation

Evan Davidson of IBM was invited to give the Keynote - a
talk entitled "The Semiconductor-Packaging Partnership". This
was a discussion of the major thrust of the silicon technology
people for System-on-a Chip, and the recent perception that
that would not work. Rather than looking at the roadmaps that
project higher and higher density of silicon chip, it is now
pretty well accepted that SoC is more costly , has terrible
yield, is much more difficult and poorer performance when
compared to a System-in-a-Package MCM approach.

But that is not the only approach being considered.
Evan discussed the INTEL BBUL approach, an update of the GE
Chips-First approach (and reminiscent of the Fraunhofer Chips-
in-Polymer technology. The chips are embedded in adhesive on a
substrate, and metallization interconnect is deposited on the
surface.

This is a major change for INTEL, and will take years to
develop the supplier base and the implementation of the
technology. In the meantime, System-in-a-Package uses smaller
chips with high yields, copper interconnect with good
propagation delay, and thus lower costs and improved performance.

Evan has written of this trend in the past, but he will
develop this in published form in the forthcoming IMAPS Emerging
Technologies Book "Foldable Flex and Thinned Silicon Chips" to be
published this summer.

Session I Optoelectronic Packaging

David Haas of Sanmina talked of "The Evolution to Optics
in Printed Circuit Boards". He said that copper interconnections are good up to 10 GHz, and then just cannot perform.
Optical interconnects can be used as low as 1 GHZ, but can have
processing speeds up and beyond 100 GHz. 1GHz to 10GHz is the
overlap region.

Never use optical interconnects if copper can do the job.
Optical interconnects for short first level packaging is never
cheaper than copper, just better at higher frequencies.

Sanmina is working to extend the copper interconnect to
10 Gbps over backplane distances of up to 30 cm. But clearly at
the higher speeds optical interconnects will be the choice.

He discussed the copper interconnections, materials, via
formation terminations and mass fabrications. One interesting
little trick was to reduce the inductance inherent in a via by
back drilling the via to take away the extended length of the
via that goes beyond the connection from the surface to the
appropriate inner layer. Interesting.

When optical interfaces are to be in the board, test the
inner layer prior to laminating any other layers over the
optical interconnects.

He also mentioned the capability of the Sanmina Costa Mesa
Facility ( formerly Allied Signal ) to produce thin flexible
LCP flex material. This facility is underutilized, but can
process Kuraray, Rogers and Foster-Miller material using
sputtering of the copper for adhesion. Since the recent 3-M work

clearly shows that sputtered copper provides the best circuit
adhesion to LCP flex, this is an important contract facility
ready for use.

As I write this there is increasing need for contract
facilities making flex. Sheldahl has filed for Chapter 11, and
that capability might soon be lost just at the time when high
density flex is much needed.

Paul Magill of JDS Uniphase spoke of "Hybridization vs.
Monolithic Integration of Optoelectronic Modules". It featured a
discussion of transition from packaging of discrete components
to hybrid or monolithic integration of the same devices. The
integration brings down the cost of the optical devices but the
two solutions, hybridization and monolithic packaging have to be
examined and their advantages determined.

Hybrid solutions provide immediate integration, and
with appropriate assembly platforms, high performance can be
obtained with efficient low cost processes that can be scaled to
high volume with automated assembly. Desired functionalities can
be provided in a single housing.

Monolithic integration can be even more efficient. The
elements are embedded in a single material system. The
difficulties arise from multiple functions in a single material
system. Performance can be enhanced, but yield difficulties may
be dominant. This is a reprise of the SoC versus SiP argument,
and in optics also the multichip approach performs better, has
lower yields and much lower costs.

But not at 40Gps - at that time it must go monolithic.
But one of the problems is that monolithic cannot handle
resistors and capacitors needed for the drive circuits.

The important question is not HOW to integrate but WHY .
The applications are for 25 Gps, possibly as low as 10 Gps, but
up to 40 Gps also. Some applications include undersea Monitors of
Optical cables. This is the world of planar lightguide, areal
IC interconnects, tunable Lasers.

In any event, there will be few individual packages at
the higher frequency application of optical interconnects.

Alan Huffman et al, MCNC "Assembly of 2-D VCEL Arrays
using Flip Chip" seemed to be about the use of the NTT Optobump
technology, yet that was not mentioned. Rather this was a talk
about using flip chip for chip connection. It said the usual
things: wirebonding is not a suitable process because it hinders
any possible 3D stacking, and indium bumping has poor pull
strength, etc. It also might be inappropriately reflowed during
the subsequent assembly.

That leaves press fit, using bright alloy, still Tin / Lead.
Plate the solder, reflow to move the bumps, alignment still 1
micron. With 100 micron pitch, joined devices have 99.98 % yield !

This is fluxless assembly, plasma assisted gold soldering
on a bumped sapphire substrate. Patterning is on BCB
dielectric, and the soldering process does not bother the VCELS.

( I still think the NTT Optobump is easier and a winner. )

Krishna Nair and Gen Rinne of MCNC reviewed the
"Contemporary Current Issues in Optoelectronic Packaging".
Optoelectronics are used in communication and displays, and
there are unique challenges in the interconnections area.
Drive currents are increasing and sizes are decreasing so that
there are higher operating temperatures. Electromigration can
be a problem, yet these devices have to last 11.4 years ( 100,000
hours )

Solder bumps of 25 microns at 50 micron pitch has been
proven, finer is possible, but the electromigration problem has
to be solved.

Electromigration is not cycle dependent, it is a
simple matter of operating hours. The limits are reached first
with the solder bumps. There must be no voids. Then deposit the
bumps with electroplating, using plasma technology. Tin
silver is better for life, electroplated tin / silver is even better.
Add a little Copper getting Sn/Ag/Cu. The problem with the use
of Tin lead is that the lead atoms migrate to the surface,
leaving voids.

Joe Schneider, Advent Optronics presented the "Optical MEMS
Test Challenges and Solutions". This is the world of tilting
mirror devices and deformable micro arrays.

What is needed is to measure tilt angles of 0.0003 degrees.
Of course light has to be directed at these mirrors and the
reflected light direction measured with optical sensors. The
challenge is to choose precision test methods to measure this
critical measurements. The talk was of the automatic test
methods to meets the needs of this area.

By far the newest talk for me was that of Alan
Beikmohamundi of DuPont, who presented an Overview of PLED
(Polymer Light Emitting Diode ) Displays. This is an emissive
alternate to the conventional backlit LCD displays. The active
polymer layer is sandwiched between glass plates with the usual
conductive column anodes and a back row cathode.

When energized the conjugated polymer chains conduct in
one direction with weak transverse conduction. The UNIAX
polymers act as semiconductor-like diodes, and are formed by
sandwiching the polymer between the plates.

Uniform emission is possible over the entire plate area.
To activate the display, a row of row and column electrodes is
activated, and then the activation is scanned down through the
whole display at a frequency so that the persistence of vision
blends the whole display.

This type of display is called "passive addressing" and is
easy to implement.

Advantages

Easy readability
160 degree viewing angle

No image latency so can handle moving graphics

Power consumption less than LCD displays

Display is emissive, so no backlight power

The result is extended battery life, an important
attribute for cellphone applications.

The manufacturing process is also simple spin coating
in air, no need for high vacuum processes.

Device testing had been monitored for 14,000 hours, and
predicted lifetime is expected to be 200,000 hours ( 20 years
continuous display more than adequate ).

This is green polymer molecules on a black background
- a return to the older and easier to read green on black. A
3,000 pixel display with 25% of its pixels on at any one time
will be operating at a power of 15 mW ( emissive power ).

Session 6, Planar Optical Interconnect

While the second optical session was on the last day, I
review it here for continuity with the first optical session.

Harry Charles of Johns Hopkins picked up after the DuPont
talk with a presentation on "Planar Lightguide Formation Using
Standard and Electro Optic Polymers". Conventional planar
lightguides can be formed from a variety of polymers that have
excellent low loss characteristics ( for example <0.2 db.cm at
800 Nm ). Quality and thickness control are excellent, and
patterned with photolithography and lamination methods make for
low cost optical medium for board level interconnect.

Construction involved cladding or a core material of high
index with low index overcoat. Substrates can be silicon,
ceramics, and polymers, even thin flexible layers.

Photoactive Polymers can be used also. The polymers are made
electro-optic by doping with optical chromophones and the
aligning the chromophones with a strong electric field to
produce a change in index of refraction. The changes are small,
but they are sufficient to produce lightguide effects.

He went on to describe various lightguide configuration
using combinations of doped and undoped polymer resins with/
without poling. ( molecule alignment with high appllied electric
field )

The resin was Ultrdel, ( You can't dope BDB ) and the
poling effect is made permanent by poling at high temperature and
then cooling. Doping drops the index from 2 to about 1.6 .
Substrates of BCB and polyimide were used. 200 F relaxes the
frozen in orientation, but performance at 125 F was OK.
there were no planarity issues.

The electrooptic behavior was comparable or better than
conventional guides.

Bruce Booth of Optical Cross Links did a marvelous
overview of "Packaging issues for Polymer Waveguide Processing".
This was a talk concentrating on the processes materials and
configurability and connectivity. He discussed their impact on
environmental issues.

I learned one thing - Alcohol destroys the polymers used for
optical waveguide - don't spill your drink ! The Boeing funded work
was on splitters, couplers and filters. Unfortunately as with
all overview talk, there was too much input for adequate notes.
It is obvious that he is an experienced worker in this area
(formerly DuPont ) and a great source of information. I will try
to get him to produce an article for some issue of Advancing
Microelectronics.

Joyce Kilmer of Symorphix went further to discuss monlithic
integration of optical waveguides and planar optical components
to improve the planar waveguide circuits. The work was to
incorporate Amplifying Integrated Components ( APICs ) into
planar waveguide circuits. Erbium ions can be doped into SiO2
based waveguides to create Er doped waveguide amplifiers. These
can compensate for the losses in the planar waveguides, often
measured in db/cm instead of the low losses associated with
optical fibers where the losses are db/meter.

Only by providing boost to the light can serial integration
of multiple functions such as taps/ splitters. switched VOAs
WDMs ( AWGs ) be provided in a PLC. ( Where does an alien
register to understand these acromyms ).

This is technology with lots of little amplifiers. If the
amplifiers work, then possibly power integrated optics can be
stacked also.

Eric Montgomery, Northrup Grumman Interconnect
Technologies, "Advantages and Disadvantages of incorporating
Fiber and Polymer Optical waveguides on or in printed circuit
boards", focused on the use of optical interconnect to get beyond
the barriers of high speed copper interconnect. Bruce Booth
gave the talk The most interesting thing was the I/O technology.

These are optical waveguide lines with separations of as
little 4 Microns, with no crosstalk

The flat planar waveguide is sandwiched between two organic
layers. Many polymers can be used except Kapton does not work
because if its moisture uptake. The connections are made by
cutting slots at the edge of the waveguide layer of the board
before the laminating, so that, when viewed from the edge, there
are a series of slots in the edge of the board, lined up with
the waveguide paths. A fiber optic connection can be plugged in
these slots for the I/O.

A special connector is used, and they are not cheap -
presently $ 260 per connector. If horizontal edge connection is
awkward, the flexible board can be bent up at a 90 degree angle
to the rest of the board, or mirrors can be used to make the
output vertical.

Theresa Sze and others from Sun Microsystems San Diego
Research talked of "Optical Interconnect Challenges in the
computer backplane". She said that with the advent of VCSEL
technology for the input and advances in materials some people
think we are on the verge of wide-spread usage of optical
backplanes. She thinks not ! She sees technology challenges that
need to be overcome for this to happen.

Not only are there difficulties in the technology but problems
with latency, power handling and bandwidth density. Her biggest
concern was reliability. She stated that present 750 to 850 nm
VCELS was "inadequate". SUN concluded that first failures would
occur in a few weeks to a few months. Reliability has to be
improved by an order of mangnitude to make the technology viable !

Richard Otte of Promex Industries also addressed the issues
that need to be addresses for optical backplanes to succeed.
He discussed the energy considerations, the functions to be
performed on the optical backplane, and the particular
challenges of the 45 degree interface needs. How do you get
from the VSCELS vertical input to the horizontal planar
lightguide. How DO you provide the 45 degree mirror surfaces in
proper register and with proper accuracy.

The problems of the connection of the VCSELS to the planar
waveguide have been solved ( c.f. The NTT Optobump interconnect
to planar optics ) but there is not yet a preferred solution in
the US.

There are three methods of forming the 45 degree ends of the
waveguide runs. The waveguide runs could be embossed into the
plastic of the planar coating by providing 45 degree ends.
Alternatiely the location of the 45 degree by milling with a saw
with the necessary 45 degree form of the saw.

The 45 degree cuts were made with an Excimer laser beam at
the necessary angle to the surface. After any of these cuts, the
ends are metallized to form the mirrors needed.

Bob Markunas of Ziptronics talked of "Wafer Bonding for
Foundry-based MEMS Encapsulation and 3-D integration". The
trend to on chip integration using wafer scale processing is
now threatened by increasing complexity. Escalating die size,
increasing functions now required ( RF circuits, MEMS, DRAM non-
volatile memory are now being desired on the "menu". How to cope
with these new demands ?

They call this wafer scale, but increasingly they use
surface mounted single die 3-D optical MEMS arrays and SAW
devices In one example they integrated ( surface attached ? )
a 4 Mbit non-volatile memory array onto a logic array.

Following that integration, the interconnect structure and
the top level of the memory are separated by 6 microns of
dielectric and connected with conventional via / trace technology.

The resultant wafer is then diced, handled, and
packaged conventionally. The result enables the different
elements of the final circuit to be made on separate process
lines, and the KGD problems are decreased because the elements
are smaller and more manageable.

They even deal with the huge size of the desired circuits.
They break the circuit into two, test separately, and then
combine.

Wow ! This is System in a package moving to System on a
Chip, but with a major difference ! There is no longer any
attempt to do all the processes on a silicon wafer for RF
analog, memory, microprocessors, etc, but to bond on minichips
onto the substrate at the wafer scale level before dicing. Each
diced section of the wafer is then a mini-SiP MCM.

Of course Wafer scale prople would not admit that this is
MCM work or SiP but that is exactly what they are doing here.

That questions are economic. Can this mini-bonding process
be done at the wafer level at costs comparable to the more
conventional SiP processes. An interesting question, needing
economic analysis and risk evaluation.

The final talk in the Advanced Packaging and MEMS packaging
area was from Dan Amey of DuPont He makes the point that
ceramics technology is not just for military and space but
recently has exploded into wireless and photonics applications.

This is well known technology, particularly using
Fodel (tm) technology. There is increasing need for thermal
vias, because the Alumina is such a poor heat conductor.
Technology is 3 mil line and space , wet etch and ion etching
both. Signal attenuation is as good as thin film technology.
They are going to Aluminum Nitride more and more for the future.

Various technologies were reviewed - Photoimageable
dielectric tapes, embedded passives, Fiber optic packages and AlN
conductors.

Medical / Bio Packaging

This session seemed like a good idea - to focus on the many
packaging aspects of medical engineering. It proved to be
particuarly difficult to bring to the table. People would
accept, then think it over and decide that in times of limited
travel money, they would rather present at a medical conference.
Unfortunately, in doing that much of the packaging is lost - the
emphasis is on the innovation of the technology in the medical
applications sense.

We had 7 papers at one time for this session, till the
speakers dropped out like flies in October. we were left with 4,
one of those was a re-presentation of the packaging of
Fraunhofer Medical devices previously given without Proceedings
at Reno ICAPS. The three others were:

Mark Johnson, of Biotronik, presented "A wireless
Communication System for Implantable Medical devices" This
development of an RF wireless communication function on the
implantable pacemakers enables pacemaker control and
defibrillation function to be controlled from outside the body.

Not only can the doctor adjust the operation of the device,
but it can signal current function to the external monitor, and
can alert to the need to changes in the operation of the
pacemeker.

The circuit design is rigid flex with micro vias and chip
scale packaging. RF power consumption was minimized to provide 5
year battery life. Median transmission time from the patient to
the physician of less than 90 seconds ! Over 100 such devices
have now been installed after the first one on October 22, 2001.
Transmission success rate is 92.3 % Approval was accomplished
from the ?FDA, FCC, ANSI and compliance with the Health Insurance
HIPAA act. A considerable hurdle race successfully navigated.

In many medical applications microelectrodes are implanted
in the body, some connected with flexible ribbon cables.
Insulating barrier coatings are needed to preserve integrity in
the body fluids,

Helmut Eckardt and others organized a presentation on the
Insulating Barrier coating for these devices Spin -on
Polyimide is the technology that protects flexible ribbon cables
from long term exposure to in vivo environments. The flex cables
were Kapton with gold conductors . Exposure to 2 years of
saline solution at 37 C maintained excellent dielectric
performance. The coatings are multilayer, 2000 Angstroms thick.

They have also used gas plasma deposited polymer coatings.
These may be more suitable to coating the implantable devices for
body use.

The remaining medical talk was more of a packaging
technology talk by Harry Charles of Johns Hopkins University,
the talk "Precision bone and muscle Loss Measurements in Space
using ANPDXA Techniques".

Because of the wasting of bone mass and muscle capability in
space, the performance of the body must be monitored frequently
to determine if the exercise regimens are working, and if the
astronaut must be returned to earth.

Conventional Ultrasound and DXA ( Dynamic X-Ray Analysis ? )
is not good enough. Only regional averages that obscures
structural details. Bone mineral Density from multiple images
are generated to give specific coverage to bones and muscles.

The equipment was designed to have minimal mass ( 46 Kg )
It still was able to detect less that 5% changes in muscle
mass and changes of only 1% in bone mass.

This equipment and technology can be used for analysis of
bone loss in the elderly and of use for injured people here
on earth.

Session 5 Signal integrity

Paul Franzon of NC State University was to present work on
a 4 Ghps High-Density AD coupled Interconnection technology,
but he was a no show. In this work, AC interconnects are used
to enable high gigabit communications with either series
capacitors or with inductive coupling elements. Capacitive
coupling gives better performance when there is sufficient area
to dedicate to the coupling capacitors in the top level metal of
each IC.

Alternatively, with only a slight increase in circuit
complexity, Inductive AC coupling can be used to bring pad
pitches down to 75 micron and maintain controlled impedance
connections.

Buried solder bumps are used to provide the DC connections
without elevating the mating substrate too high for the
inductive or capacitative couplings. The structures have
successfully produced interconnect structures.

Clay Cranford of IBM RTP NC talked of "High Speed SerDes
Designs" The important information was that semiconductor
device cells as signal drivers and receivers can bve included in
FR 4 PCBs and can send signals at 2.5 Gb rates ! Competition
for planar optics !

The cells were proposed as standards for IBM circuits, each
pair multiplexing / demultiplexing for 655 MB.sec data streams.

Jay Diepenbrock of IBM RTP discussed "Future Trends in the
Electrical Performance of Connector Systems". Information
technology is changing and IBM with it. IBM now buys 51% of its
systems, and that will be greater with the sale of the Endicott
facility and the transfer of the high end main frame work of
Poughkeepsie to Hitachi. They are therefore more and more
concerned with the establishment of standards for evaluation of
everything, including connectors.

There are presently too many test standards and much
confusion about performance. The talk focused more on the need
for established procedures and testing that on the actual design
of the connectors.

Conclusions

By any standard this was a successful workshop. The optical
presentations were complete and varied. First level planar
optics and backplane interconnects are the area to be compared
with electronic packaging technoogy.

It therefore is directly in the purview of the
Systems Packaging committee.

Medical Packaging presents a challenge to bring to the
electronic packaging world, but the concept of having the
workshop in Research Triangle Park was a success.

It was decided that next year's workshop will be held again
at RTP. but the date changed to mid June to avoid the conflict
that is happening as 6 other workshops and meetings have moved
to our traditional mid-May time frame. There is a problem with
June - ( Europe is on vacation ) but this had moved back to a
predominately US workshop with little European participation..

A worth while meeting.

JW Balde 7/01/02