EDAPS - TC 12 Workshop

A one day workshop on Electrical Design of Advanced Packaging & Systems (EDAPS) was jointly organized by IEEE ED/CPMT/ Reliability chapter, Institute of Microelectronics (IME), Singapore and Ga Tech Packaging Research Center, USA on 9 December 2002 at IME auditorium. The workshop, first of its kind in Asia was co- chaired by Mahadevan K. Iyer ( IME, Singapore) Tohio Sudo of (Toshiba Corporation , Japan) & Prof Joungho Kim of (KAIST, Korea).

Aimed to enhance the awareness of package and system electrical design concepts, issues and challenges ahead for next generation microsystems in this region ,the workshop had 80 registered particpants from Asian countries such as Malaysia, Philippines, Indonesia, Korea & Japan. There were nine invited technical talks by eminent researchers from US, Europe & Asia in the field of electrical design, modeling, test and measurements for advanced packages, modules & systems.

Prof Rao Tummala, President ,IEEE CPMT while inaugurating the event, addressed some of the key challenges ahead for system designers. Dr Lim Thiam Beng, Deputy Director of IME while welcoming the speakers & attendees mentioned the importance of this workshop in Asia.

Prof. Kanji Otsuka (Mesei University) in his key note talk presented an in-depth analysis of differential signalling and the importance of maintaining TEM wave mode in the GHz environment for electronic packaging. Prof Andreas C. Cangellaris (University of Illinois) gave an overview of the EM modeling and discussed trends and needs for substrate noise coupling, global power grid modeling and EMI modeling with case studies.

Dr. Gen Murakami (Hitachi Cable Ltd) in his talk discussed high transfer speed packaging technology, using a novel Micro Interposer Tape Technology. Jong-Gwan Yook (Yonsei University) discused the design issues in a power distribution network in particular for arbitrary shaped systems. A decoupling capacitor methodology was illustrated.

Picture of J.G. Yook Gen Murakami

Prof F.G. Canavero (Polytechnic University of Turin) presented a macro-modeling method for system-level EMI-EMC assessment and the application of a RBF (Radial Basis Functions) model for conductive & radiative coupling. Dr. Y. Sugaya of Matsushita Electric Industrial Co. Ltd gave an introduction to a new 3-D System in Module SIMPACTTM and explained how the technology would enable to embed discrete devices into laminates.

Pictures of David C. Keezer, Ga Tech Y.Sugaya Matsushita Electric

Prof David C. Keezer (Georgia Institute of Technology) shared the Test Strategies for High Density Packages and discussed novel test methodologies for wafer level testing. Dr Bruce Archambeault (IBM,) discussed the importance of decoupling power and ground analysis with two applications viz: functionality for transient response and EMC for steady state response. Prof Joungho Kim (KAIST) provided a detailed analysis for Gb/s enhanced eye-pattern of BGA type board-to-board connector and this work is driven by the challenges faced in implementing Gb/s signaling on PCB.

A panel discussion chaired by Prof. Madhavan. Swaminathan (Georgia Tech) laid the platform for a lively exchange of questions and answers on the design challenges for system integration in the future.

It was indeed an intense day packed with enormous amount of information. The event provided a congregation of research and industry professionals and provided a platform for exchange of information and ideas.

B. Archambeault (IBM) & Workshop Chair M. Iyer (IME) with TC 12 Chair M. Swaminathan (Ga Tech)