There were 14 half day Courses offered at the beginning of the ECTC week. More than 260 eager engineers attended at least one. Such course work goes into depth in either a fundamental or a cutting edge technology used in the packaging/assembly industry. Each course is packed with information, so the typical student absorbs only a small percentage that their experience has prepared them to learn. This little slice helps make the student a better professional. Continued Education credits can be awarded with these classes as a way to document the accomplishment on your resume.

With that in mind a few courses will be reviewed from the perspective of one student.

Hassan Hashemi taught a morning course entitled "Advanced Organic Substrate Package Design & Manufacturing for RF & Broadband Applications." Twenty students listened to and dialogued with his presentation. They came from around the globe and most were from industry. The teacher had much experience in RF board design and manufacture support at Rockwell Science System and now Mind Speed Inc. The student copy of the slides had many hard to find tables of material properties which would aid many design decisions and simulations.

It is the explosion in Wireless and Telecom Industries that have resulted in the drive for integrated, small, cost sensitive RF systems.

There were discussions on relative cost of organic RF boards versus ceramic. For large production runs of commodity product economy of factor of 4 were mentioned. However, as the organic board suppliers are being squeezed by market forces ceramic premiums of 20 - 230% are more typical.

The trend for the big markets (cell phones and PDAs) is to put the whole system (including RF power amplifier) on one board. There are still some markets where PAs are built on ceramic (Hitachi). Three stages of integration are being pursued. (1) packaged discretes on a hybrid board, (2) bare chips on a MCP, and (3) so super integration like SiP or SoC. Some of the first MCPs were multiple chips on the same leadframe to use manufacturing infrastructure already in place.

In all three cases you need very good CAD tools with excellent libraries. In the case of the new SiP and SoC approaches the tools do not really exist and the NRE cost are $0.6 - 1.0M. As frequency is increased the designs are less tolerant to having plating stubs on the conductor runs so electroless plating is increasing in use.

When doing the design, split it up into function modules and simulate and prototype each module to check for EMI/EMC since you will never solve these problems on the system level if you don't have a handle on them at the module level.

There was much discussion of integrating passives in the design. Several rules of thumb were suggested. The first was to look the designer in the eyes and say "you have to be kidding about the number of discretes you want to use…cut it to one third." The second was that using interconnection paths to make inductors often gains in performance, whereas resistor and capacitor chips are often the best way to go. As a designer one must be flexible even during the first build…often the values of discretes must change at the last minute.

Most organic boards have higher RF transmission losses than Ceramic, but some of the latest expensive organic materials (such as PTFE) are slightly better than ceramic. Flex substrates have not been used as much as predicted 10 years ago. This is partly because the frequencies are getting higher and flex gets lossy, and partly because flex companies are not prospering in any of their business lines.

When asked why most of the history of the RF board business is a story of incremental changes, Hassan responded that the market only has room for such improvements. Any breakthrough materials or geometries will need someone with deep pockets outside of the product shipment business…maybe dedicated universities or government labs.

An afternoon course entitled "Packaging Challenges for 10 Gb/s and 40 Gb/s ICs" was taught by Roberto Coccioli and Hassan Hashemi. About 30 engineers attended.

The challenge is that the device cost is much less than the packaging cost for this temperature range. It has become the roadblock for this telecommunication market. Today's limitations for this high bit rate can be listed as (1) packaging capability, (2) fast/efficient devices, (3) integration design, and (4) customer demand (recession).

The designs are dominated by optical communication protocols since this is the first large market to need (or think it needed) this high rate communication. The circuits are made either on ceramic (materials choices good to 40 Gb/s) and organic boards (organic composite polymers). A big process problem for thick film on ceramic is the control of the line width dimension to maintain a design impedance. Another problem is that for good ground planes at these high frequencies a 75% mesh is needed, but 50% mesh are what is typical for trying to prevent layers from delaminated.

Although bump bonding has higher performance, much of the assembly is done with clever implementation of wire bonds. If kept short, signal wires surrounded by ground wires, double wires replacing single, and capacitive pads used to cancel induction of wire…than wire bonding works to 50 Gb/s.

Designers now have the option of SiGe ICs but with x10 the NRE of GaAs designs. At lower frequencies enhanced Si CMOS design is gaining ground, but not yet at this higher bit rate range.

Connectors into and out of the modules must be designed for performance and for reliability since the exacting tolerances can not survive too many matings and temperature cycles.

Signals on the board must be sent along defined impedance paths such as microstrip or ground backed coplanar waveguides. The design needs computer simulation with codes such as HFSS or Cadence's Specter simulator.

With these great challenges to the engineer, perhaps there is a silver lining to the several years of low demand in the market. Perhaps design and process problems can be solved not just worked-around.