On the first night of this year's ECTC before attendees found
out the hotel was walking distance from the jazz clubs of the
French Quarter, a well attended panel session was held on Trends
in Advanced Packaging and Manufacturing Development.
Dr. Shluh-Kao Chiang of Prismark talked of "subcontract leadership".
He mentioned that everyone wants to be the technology leader but
no one wants to pay the price--Particularly in today's market
of low margins on most products. We need more leadership today
in the past since we have been living "disintegration"
over the last decade. That is, the system design, the foundries,
and the testing are often done by separate companies in separate
countries. He asked "who will carry the future since packaging
is very complex."
He identified the system innovators as (1) Intel and IBM for CPUs,
(2) TI for DSP, and (3) RFMD and Conexant in SiP. This innovation
requires a sustained specific product focus in technical and commercial
development.
A few years ago IC revenue was $121B. Of this 13.7% represented
packaging/assembly/test. Of this 31% was outsourced and 69% captive.
By the year 2007 he saw the market growing to $225B with $30B
in packaging of which 38% is performed by merchant services. Currently
the big three (Amkor, ASE, and SPIL) perform more than 50% of
the merchant business. But the tough market recently has only
a 12% margin so these companies can only apply 2% of their flow
to R&D. This leads to clever evolutionary change making our
industry look like mature.
In contrast, the historic IBM had a longer term perspective and
could think about the manufacturing technologies needed 5 years
down the road. However, today with the realities of the marketplace,
vertically integrated manufacturers like IBM and Agere only spend
about 0.4% of revenue on long range packaging development. Companies
that have some captive ability but rely on sub-contracting (AMD,
Intel, TI) spend about 0.3%. In contrast the subcontract assemblers
spend 1.5 - 2.5 %. Fabless companies such as Altera, VIA spend
less than 1% today but may put more in the future.
John Nickelsen, VP Sales of ASE, made it clear that their R&D
was driven by the immediate needs of their customers. He pointed
out that using this approach the advances made were dramatic.
For example, in 1991 their operation could be typified by 208
lead QFPs. However, by 2005 the complexity will have increased
by a factor of 15 through the use of 3000 lead SiP. In addition
flip chip has increased in use by a factor of 4 in the last few
years. The lead frame solution is giving way to the flip chip
and wafer level packaging. He sees the single chip solution in
certain key markets but other products will need SiP development.
His shopping list included: embedded components in substrates,
Pb-free bumping, Pb-free BGA flip chips, stacked die for SiP,
Chip on Flex, ultra thin BGAs (3mil thinning of 8" wafers),
and low strain opto/MEMS. He saw KGD as key to SiP and more development
needed there. He noticed a trend for WLP to replace low pin cout
packages.
Their business goal must be to shrink the cost of packaging as
a percentage of final product price. Electronics moved into the
realm of commodity but still has much room for targeted R&D
to give the market edge.
Mario Bolanos, director of TI semiconductor packaging, maintained
that TI still supports a strong internal packaging development
but could not try to do everything themselves. They focus on R&D
for their Key Markets. One challenge is to protect the fragile
copper/low-K interconnections on advanced ICs. TI develops test
die that minimize the development cycle times once the final product
die is ready. He sees TI concentration on high performance die:
20 mm, >100W, 10,000 bumps, pitch of 150 micron, ultra-low
alpha emitter underfill material, bump current density >100,000,
wireless output, and possible stacked chips.
In general, Mario suggested to the audience that real systems
houses develop the chip, package, and board simultaneously…not
just with view graphs but with manufacturing development. TI is
currently doing 20% inside and 30% external. They try to achieve
10% impedance control by computer modeling.
Tom Gregerich, Qualcomm Wireless, listed "Contemporary Issues
in IC Packaging Engineering for Wireless Products:" (1) rate
of technology introduction, (2) increase in level of product complexity,
(3) unpredictable market and less development time, and (4) tech
focused but cost driven.
He sees customers using discrete solution when ever it is cheaper.
This is particularly true since time to market is usually the
dominate force and integration takes more time.
He sees Intellectual Property as become a more important issue
since fewer centers are developing the new packaging/manufacturing
technologies. However, since the technologies are getting more
complex it has become harder to prove that someone is copying
your IP and not just an example of Darwinian parallel development.
He sees room for both SOC and SIP in the future. The audience
believed that in general the materials companies would continue
to develop the packaging materials since the market will continue
to expand. However, it was pointed out that no material makes
real money for about 10 years and then only if it spins out many
other daughter materials along the way.
picture 1: Tom Gregerich (Qualcomm Wireless) and Shluh-Kao Chiang (Prismark)