Electrical
Design of Advanced Packaging and Systems ( EDAPS) 2003
2nd Asian Workshop on Signal Integrity
Date: November 10, 2003 ( Monday)
Workshop Location:
Uri-Byul Seminar Room
KAIST ( Korea Advanced Institute of Science and Technology)
EECS Department
373-1, Yusong-gu, Gusung-dong,
Daejon, Korea
Contact Information;
011-82-42-869-3458 , or 5458
FAX) 011-82-42-869-8058
Email) teralab@ee.kaist.ac.kr
Joint Organizers:
KAIST BK21, IEEE CPMT, CEMP, Korea Microwave Society.
Technically sponsored by: IEEE CPMT TC-12 Subcommittee on Electrical Design, Modeling and Simulation.
Objective:
The EDPAS Workshop is to enhance the technical awareness in the
Asia region specifically in area of package and system electrical
design concepts, issues, and challenges ahead for next generation
electronic products.
Program Committee:
Chairman: Joungho Kim, KAIST, joungho@ee.kaist.ac.kr
Co-chairs: Mahadevan K. Iyer, Institute of Microelectronics,
iyer@ime.a-star.edu.sg
Toshio Sudo, Toshiba Corporation, toshio.sudo@toshiba.co.jp
Program Committee :
Yu Jin, KAIST, jinyu@kaist.ac.kr
Choi Min Sung, KAIST, mschoi@kaist.ac.kr
Lee Jongjoo, Samsung Electronics Inc. jongjoo.lee@samsung.com
Heeseok Lee, Samsung Electronics Inc., hees.lee@samsung.com
Jonghoon Kim, Samsung Electronics Inc., jonghoon@mail.kaist.ac.kr
Wee Jae Kyung, Hallym University, wjk@hallym.ac.kr
Jongwan Yook, Yonsei University, jgyook@yonsei.ac.kr
Park Sung Min, Ulsan University, smpark@ee.ulsan.ac.kr
Lee Choon Heung, Amkor Technology Inc., cdlee@amkor.co.kr
Paik Kyung Wook, KAIST, kwpaik@sorak.kaist.ac.kr
Kwon JongHwa, ETRI,
Lee Hee Jai, Samsung Electronics Inc., jhlee109@samsung.com
Choi Chul Seung, Samsung Electronics, Inc., clschoi@samsung.com
Hong Yungsoo, Samsung Electronics Inc. frank.hong@samsung.com
Hyunjung Park, KAIST, angel820@eeinfo.kaist.ac.kr
Myunghoi Kim, KAIST, mhkim@eeinfo.kaist.ac.kr
Jongjoo Sim, KAIST, inteluna@eeinfo.kaist.ac.kr
Speakers:
Madhavan Swaminathan, GaTech, USA, madhavan.swaminathan@ece.gatech.edu,
(Title: Modeling of Switching Noise in Modern CMOS Systems - A
Systems Perspective)
Mosis Cases, IBM, USA, E-mail: cases@us.ibm.com
(Temporal title; System Packaging Design Challenges for High-Speed
Serial Links)
Tapan K Sakar, Syracuse University, USA, E-mail: tksarkar@yahoo.com
(Title; Towards A New Unconditionally Stable FDTD Method Without
The Time Variable)
Woonghwan Ryu, Intel, USA, woong.hwan.ryu@intel.com,
( Title: Design Challenges in Giga-Hertz Bandwidth Digital Interfaces
)
Flavio Canavero, Politicino di Torino, Italy, canavero@polito.it
(Title: Macromodeling of connectors and packages with a large
number of ports)
So Byung-Se; Samsung Electronics, Korea, bs.so@samsung.com
(Title: Design of Next Generation DDR Memory Module)
Kim Yongjoo, Hynix, Korea, yongju.kim@hynix.com
(Title: A Path-based Equivalent Circuit Model Based Design Method
for Power Distribution Networks of High-speed Digital Circuit
Systems)
Choon Heung Lee, Amkor Technology Inc, Korea, chelee@amkor.co.kr
( Title: Future Packaging Technology in Amkor- packaging and material)
Jongjoo Lee, Samsung Electronics, Korea; jongloo.lee@samsung.com
( Title: Effects of Package on the Signal Integrity and Power
Integrity of DRAM)
Yuji Shirai, Association of Super-Advanced Electronics Technologies(ASET),
Japan
(Title: 3-Dimensional Chip Stacking for SOP Solution )
2 more speakers from Japan. ( Will be decided in two weeks)
3 speakers from Singapore. ( Will be decided in two weeks)
1 speaker from China.