29th International Electronics Manufacturing Technology Symposium
to be held as the
SEMI Technology Symposium
(STS: IEMT) at SEMICON West

July 14-16, 2004
San Jose, California

CALL FOR PAPERS
Semiconductor Equipment and Materials International (SEMI), and IEEE Components, Packaging, and Manufacturing Technology (CPMT) Society invite manufacturing professionals from around the world to submit abstracts to STS: IEMT at SEMICON West 2004. STS: IEMT continues to be one of the leading technical conferences for discussing solutions that improve the electronics manufacturing process. For equipment and materials suppliers, and device manufacturers, STS: IEMT provides unparalleled opportunities for both electronics and microelectronics professionals to network and learn the latest in manufacturing strategies and methodologies to achieve manufacturing excellence. Abstracts are peer-reviewed and are selected based on a clear outline of problem, analysis, solution/results and conclusion. Presentations on original, non-commercial and non-published works are being solicited in the following areas:

3D PACKAGING

TEST, ASSEMBLY AND PACKAGING ADVANCED MANUFACTURING PROCESSES

ADVANCED MATERIALS AND RELIABILITY

ENVIRONMENTALLY FRIENDLY MANUFACTURING (CFM):
Ultraclean technologies; Clean materials; Mini environments; Environmental factors; Carrier influence; Recyclability

COST REDUCTION:
Cost management; Cost of ownership; Benefit of ownership; Justification/ROI for capital expenditures; Supplier/Customer continuous improvement programs

TEST, ASSEMBLY AND PACKAGING FACTORY DYNAMICS:
Continuous improvement processes; Qualification strategies; Extending current capabilities; Manufacturing line performance; Methods to determine capacity components and magnitudes; Capacity detractors and analyses of causes for detractors and cycle time losses (tool, operator, WIP, etc); Cycle time and fabricator load/capacity relationships; Activities undertaken to reduce capacity detractors; Deployment and implementation of work method changes into manufacturing, EMS/IC assembly, Semiconductor assembly

WIRELESS AND OPTICAL NETWORK COMPONENT AND SYSTEMS MANUFACTURING TECHNOLOGY:
OE/EO components and assembly; RF, Planar and Other lightwave circuits manufacturing and packaging

ADVANCES IN WAFER LEVEL AND CHIP SCALE PACKAGING:
Wafer bumping; Photolithography challenges; Singulation; Wafer breaking/scoring; Overmolding; Redistribution; 300 mm manufacturing challenges; Wafer thinning; 3D assembly

TIME-TO-MARKET:
Design for manufacturability (DFM); Technology transfer; Quality functional deployment (QFD); Early manufacturing involvement; Theory of constraints (TOC)

YIELD ENHANCEMENT:
Wafer level/Board level inspection tools and techniques; Defect inspection methodologies; Wafer level reliability (WLR); Failure analysis; Yield modeling; Process defect reduction; Defect reduction in materials; Defect-to-yield correlations; Design for manufacturability; Product Yield Risk Assessment (PYRA); In-line inspection; Intelligent data analysis; Systematic yield problems

PRODUCT TEST AND TEST PROCESS OPTIMIZATION:
High speed testing; High bandwidth; Mechanical probing; SOC; SIP; Structural testing; Dynamic burn-in

OFFSHORE VS. ONSHORE MANUFACTURING:
Technology transfer and resources; Local content; Culture/Language barriers; Maintaining yield; Fabless and manufactureless

MEMS/MOEMS TECHNOLOGY:
Manufacturing techniques; Novel materials and problems unique to specific projects; Meaning of volume manufacturing to MEMS suppliers; Implications of using smaller wafers and older tools

PANEL DISCUSSIONS AND/OR WORKSHOPS

SUBMISSIONS:
Papers co-authored by a user and a supplier and/or academia that address practical solutions to real problems are highly encouraged. Abstracts are welcome from all those involved in electronics manufacturing including: merchant and captive IC manufacturers, equipment and materials suppliers, packaging foundries, contract assemblers, and academia and research institutions.
Prospective authors are requested to submit the following by February 7, 2004: a 250 word abstract, paper title, author name(s), company/affiliation(s), a 25-word biography of the principal author, and primary contact information. Because correspondence is conducted electronically, e-mail address is mandatory. Authors selected to present at the conference will be notified via e-mail by mid-March. A final camera-ready manuscript in MS Word file and IEEE copyright form must be submitted by the determined due date to be published in the STS: IEMT 2004 proceedings and in order to present at the conference.

Please submit your abstract to the following:

Online:
www.semi.org
or
www.cpmt.org/iemt
E-mail to:
techspeakers@semi.org
Please note subject line: STS: IEMT 2004 Abstract Submission
Postal mail or for further questions:
Gloria Lou, Program Coordinator
SEMI
3081 Zanker Road
San Jose, CA 95134 USA
Phone: (408) 943-7048
Fax: (408) 943-7913

Membership in SEMI or IEEE is not required to present a paper or attend the symposium. Submitting an abstract represents a commitment to provide a cleared manuscript by the determined due date and to attend the STS: IEMT or send a knowledgeable representative. This attendance includes a requirement to pay for the full conference at the speaker's rate. It is the author's responsibility to obtain internal company approvals in time to meet these deadlines. Specific author instructions to assist in the manuscript preparation will be sent via e-mail upon acceptance notification. The language of the symposium and the proceedings is ENGLISH. Excerpts of your paper may be shown to the press and/or used in pre-conference publications. Specific requests not to involve your work in pre-conference publications should be made to the SEMI office at the time of the abstract submission. Papers published in the Proceedings may be considered for publication in the IEEE CPMT Transactions after peer review.