12th Topical Meeting on Electrical Performance of Electronic Packaging

The 12th. Topical Meeting on Electrical performance of Electronic
Packaging (EPEP) was held from October 27-October 29, 2003 in Princeton,
New Jersey. The meeting provides a forum for the presentation and
discussion of the latest advances in the electrical design, analysis and
characterization of on-chip and off-chip package interconnections and
structures covering all the application families and frequency ranges
namely, digital, RF, microwave and mm-wave applications. EPEP is
co-sponsored by the MTT and CPMT societies of the IEEE.

The afternoon of October 26, before the start of the conference, the
third annual workshop, sponsored by the IEEE CPMT Society, "Future Directions
in IC and Package Design", had very good attendance of 60 participants
from all over the world. Alina Deutsch of IBM Corp. and Madhavan Swaminathan of
Georgia Institute of Technology chaired this meeting that had 7
excellent international invited speakers from the US, Europe, and Asia,
that were divided into three sessions
chaired by Greg Taylor of Intel Corp. and George Katopis of IBM Corp.
The first three speakers addressed high-end processor and package design
issues. The second session covered tools and technology development
needs and projections and the third special session addressed CAD tool
development. The workshop was open to all EPEP conference attendees free
of charge.

The EPEP meeting this year was organized into twelve sessions of oral
presentations and one open forum (poster) session for one-to-one
discussions. The papers represent 9 countries (Belgium, Sweden, Korea,
Taiwan, Japan, Canada, Italy, Germany, and USA). The meeting began with
a keynote speech titled "Architecting Interconnect" by Peter Hofstee,
IBM. (Dr. Hofstee, Vice President and General Manager, Desktop
Platforms Group, IBM Corporation). Dr. Hofstee made the observation
that the optimum pipeline depth for a microprocessor has 6 to 10 fan out
4 gate delays per pipe stage. He emphasized that Machines must be
balanced for performance and power and that speculative computation is
expensive. He quoted Gelsinger's Law: "New generation micro
architectures use twice as many transistors for a 40% increase in
performance". This implies a 30% reduction in efficiency. As a result,
Dr. Hofstee sees multithreaded / multi core chips as the way of the
future with software as the major bottleneck. With a fixed core micro
architecture, I/O bandwidth needs to grow 40% per node as the number of
cores per chip doubles. This path will lead to a need for 1 TB/s per
socket at the end of the decade. Using 20% of the power budget of a 200
W chip means that we'll need I/O that runs on 5 mW/(Gb/s).

The remaining eleven sessions were dedicated to System Design and
technology, Power Distribution design and Noise, RF/Microwave,
Electromagnetic Issues, Modeling, Transmission Lines, Measurements, On
chip Issues (that mainly cover I/O circuit design, clock net design and
analysis, and electrical parameter extraction), Interconnection macro
modeling. This year, the conference also featured One session (7 papers
from industry and academia) on on-chip CAD Issues.

On Sunday October 26, Two short courses were offered prior to the start
of the meeting. The tutorials were given by well-known experts in their
fields. One tutorial covered I/O circuit design and the other
covered system power distribution.

Once again special attention was paid to graduate student attendees of
this meeting with the presentation of Intel and IBM Corporation awards
to the two most outstanding papers authored by graduate students. The
IBM award consisted of laptop and $1000 cash and the Intel award
consisted of $2500 cash. A total of 26 papers competed for these
awards. The best student paper award sponsored by Intel corporation was
given to Anestis Dounavis, from Carleton University for his paper
entitled "Delay Extraction and Passive Macromodeling of Lossy Coupled
Transmission Lines.", Anestis Dounavis, Natalie Nakhla, Ram Achar, and
Michel Nakhla. The best student paper award sponsored by IBM corporation
was given to Rohan Mandrekar from Georgia Institute of Technology for
his paper entitle "Extraction of Current Signatures for Simulation of
Simultaneous Switching Noise in High Speed Digital Systems.", Rohan
Mandrekar, Madhavan Swaminathan, and Sungjun Chun.

An industry reception for students hosted by IBM was held on Tuesday
October 28th that provided the opportunity to 14 students to get to
discuss package design issues of interest with industrial
representatives. In addition, the meeting hosted five exhibits.
Companies represented included: Intel (Israel), Optimal Corporation,
Ansoft Corporation, Sigrity, Inc, and TDA Systems.

A special issue in CPMT transactions based on the paper version of the
presentations at this 12th EPEP meeting will be edited by Dr. Tawfik
Arabi of Intel and Dr. Robert Jackson from the University of
Massachusetts.

--submitted by Tawfik R. Arabi