Phoenix Chapter Workshop Success

Thursday, November 20th, I went to a workshop on Devices, Interconnects, and Packaging for Next Generation Computing and Communication Applications at ASU in Tempe, Arizona. While embedded passives are still a hot topic, it seemed this year a concurrent theme was the tendency to go smaller and what issues are being faced in this quest for miniaturization.

The morning session was focused on devices and the first speaker was the keynote one, Peter Zeitzoff from SEMATECH and a CMOS roadmap. Moore's law was mentioned and while its focus is on device size, the real issue associated with it is increased speed and increased function density of future ICs. The International Technology Roadmap for Semiconductors (ITRS), of which Mr. Zeitzoff is an integral part, is an effort to map IC technology for the next 15 years, addressing key needs, solutions and stimulating R and D. Used to project this map is a scaling approach, where some of the targets are speed and power. Maximum speed is the inverse of the intrinsic delay, so naturally the desire to scale down this delay is key. Seventeen percent every year is the goal, set by current transistor scaling. Lower power dissipation is also desirable and is directly associated with leakage current and Vdd, two significant parameters in the scaling goal. Some solutions to these issues are high k dielectric materials to replace SiO2 (for leakage current), strained channels (speed, improves u) and metal gates (leakage current). There are a number of other avenues being pursued to remedy the many challenges presented by scaling so quickly into the sub-micron regime.

Next was a presentation on Silicon Nanotechnology by Suman Datta from Intel. Nanotransistors will allow Moore's Law to accurately predict the scaling of transistors and technology. A Pentium 4 now has about 40 million transistors, a number that is predicted to increase to about 1 billion by 2007. A 15 nm gate length transistor is projected by 2010 and 10 nm early next decade. Included in nanotechnology ideas is a 5-nm silicon nanowire ready by 2013 and offering additional gate control. New process techniques are necessary for nanotransistors and can include atomic layer deposition, high k dielectric stack, and strained silicon or metal gates. Challenges predicted are phonon interaction effects with high k dielectric materials and physics limitations on just how small is realizable.

Yang-Ki Hong from the University of Idaho addressed Trends in Magnetic Information Data Storage and MRAM. With the need for increased storage comes new development and characterization of magnetic nanoparticles and nanofilms that include CoCrPt-based alloys, self assembled CoPt and FePt. New advances in shapes of magnetic tunneling junctions for MRAM devices are being made. In addition to the already existing shapes of rectangle, hexagon and ring MTJs, Dr. Hong presented a Pacman shape that offers high switching field and the narrowest switching field distribution over the other shapes. Dr. Hong and his team at the University of Idaho are actively researching magnetic storage solutions.

Jim Teplik from the SPS at Motorola presented RF and Mixed Signal Technologies. The SiGe HBT offers high fT and a high fmax by having a thin base region and a low Rb, respectively. Graded Ge yields an improved output conductance over non-graded Ge and strained SiGe offers the lower Rb, which can increase current gain, b. When carbon is added to the structure, this helps keep the base region thin, increasing the fts. Vertical scaling was also mentioned, improving frequency performance through the base profile, collector resistance and collector doping. Integrating SiGe HBTs with CMOS was presented as an attractive technology (BiCMOS) with a low noise figure and high b, but the cost is still high. Signal isolation is also an issue of system on a chip type integration. RF CMOS was also addressed with effective length and oxide thickness being scaled now. Challenges with decreasing size, however, dominate the use of RF CMOS. Leakage current, lower gain and dynamic range are a few of the problems that affect RF CMOS. Passive structures were also mentioned for their role in matching. Although improvements have been made (metallization, dielectric materials), area is still a large concern.

Azad Naeemi from Georgia Institute of Technology spoke of Optimal Global Interconnects for Gigascale Integration. With the roadmaps predicting smaller and smaller feature sizes, interconnects have become a dominant concern as they do not scale with technology. Optimal dimensions were emphasized for small latency (faster communications) and large bisectional bandwidth (larger transfer of information). Dr. Naeemi introduced a new design approach, an interconnect-centric rather than a transistor-centric one for GSI chips. Since interconnects contribute to the limitations, the designs should center around those, focusing on optimal wire widths and aspect ratios. Optimizing these for maximum data flow and minimum energy is the ultimate goal. Issues presented include delay variation, multilevel and intra-level crosstalk and energy per bit.

The afternoon focus was on packaging and began with Nozad Karim from Amkor talking about High Speed Package Design. He emphasized the need for a design chain that considers layout, IC packaging and the final system from the beginning of a project. This is especially important when a complex package is necessary. Package selection, pre-design, and simulations are all key in reducing design iterations. Add nanometer designs and more challenges arise like capacitance, current leakage and package issues like metal pitch. Package considerations should be addressed as soon as possible for all aspects of design, power/ground structures, I/O signals, and EMI concerns. Advantages of certain packaging techniques should be known, e.g., when to use a flipchip design or wirebonds, each having their own tradeoffs. Package consideration at the start of a project helps reduce the design cycle in system on a chip designs.

Michael Gaynor, also from Amkor, addressed Embedded Passives, RF Functional Blocks and Shields. Cost reduction, routing and height reduction were the main reasons mentioned for embedded RF functions. Various laminates were discussed like Getek, LTCC, and a Getek - BT-MG combination, all of which can be utilized for RF functional blocks such as filters and baluns. They have developed a library offering filters, BALUNs and diplexers with the goal of reducing design time and lowering development costs. Getek is the preferred substrate for embedded RF functions where the functions presented were utilized for the cell phone or wireless communication industry. Embedded passives hope to offer more integration, lower cost and better reliability than soldered passives. Some of the substrates used for this are ceramic filled FR4, thick and thin films and silicon. Although highly desired, embedded passives still face challenges. Right now the tools and processes are immature which affects cost and reliability, major factors in the success of embedded passives. Embedded shielding and its desired effect of reduced coupling was also mentioned. Experiments have been done but design rules are still being defined at this time.

Hassan Hashemi from Mindspeed Technologies talked about Broadband Mixed Signal System Level Packaging, which focused on power distribution in a mixed signal system-on-chip device. Some of the challenges facing mixed signal IC-package-board design are power distribution system (PDS) simulation, deciding which design technique works well for a mixed signal design and correlating measurements to simulations. PCB PDS designs were examined and utilized for a system level and package level design. Tradeoffs between wire bonding and flipchip techniques were also discussed. Isolation and how to tradeoff the analog and digital supplies were a couple of the challenges PDS designers are faced with.

Characterization and Failure Analysis of Silicon Devices, Current and Future was presented by Dieter Schroder from Arizona State University. With decreasing device sizes, new materials and different structures, failure analysis is now more difficult. The challenge lies in determining where the failure site location is with new packaging technologies (flipchip) and increasing metal layers. Techniques discussed to locate the failures include picosecond imaging circuit analysis, voltage contrast, IDDQ testing and microprobing, among others, all of which were discussed in detail. Failures detected by some of these are gate oxide shorts, incorrect timing or slow switching, and physical defects. Failure analysis today pushes the limits of existing tools, but with the development of new tools, some mentioned in this presentation, characterization and analysis are overcoming some of these challenges.

Deepak Goyal of Intel presented Failure Analysis of Packages, first talking about typical failure mechanisms in packages. ON the 1st level interconnections, wire bond damage is fairly common with damage occurring at the neck and heel, depending on what type of bond was done. C4 interconnections can show cracks between bumps, also considered 1st level. On a package level, there can be corrosion, "popcorning" (die surface delamination), via adhesion issues and PCB cracking. Solder balls and bumps also exhibit cracks or fatigue from underfill. With the new technology showing thinner packages and more complex structures (mixing packaging techniques) come different failure mechanisms and increased difficulty isolating where the failure occurred. New techniques are being developed that include x-ray tomography, thermal imaging and laser milling all of which have their own tradeoffs. The focus of the next generation of tools is to develop non-destructive techniques.

Christopher Taylor from Strategy Analytics addressed The Road to Ubiquitous Computing, Entertainment, and Communications focusing on wireless and broadband markets. The first topic was broadband access and its increasing trend. More consumers are opting for broadband connections and seeing the advantages of doing so. This increase drives the WLAN devices in homes to share this connection; WLAN almost doubled from 2002 to 2003. This trend leads to developments in the WLAN future like home video distribution, mesh networking and WLANs connected via 802.16. 802.16 capabilities will further increase wireless mobility. UWB is also on its way up, an attractive alternative to USB for digital cameras and camcorders. The 3G cellular market is also increasing, but not at the same rate as the broadband market; consumers are not completely convinced of its benefits. These increasing markets dictate component trends with goals of lower cost, more integration, higher Ft and longer-term products. More functionality is also a goal of the digital processors necessary to complete these products and make them competitive. Though still uncertain, UWB, mesh networks and RFID are just a few of the promising technology that awaits society.

Vision for Convergence: Next Generation Computing and Communications Solutions was presented by Ron Curry from Intel. "Anytime, anywhere, any device." This was the vision presented by Mr. Curry that sets the goal that a user will have access to information or services at any given moment and place. Micro and macro convergence is when computing and communication come together on both small and large scales. Micro-convergence offers integration with reduced cost and new capabilities. This leads to macro-convergence that produces new businesses, infrastructures, and new societal norms. New devices like sensors, and areas of technology like silicon photonics, fluidics and healthcare are being enabled by the marriage of computing and communications. Convergence is accelerating and with it comes new and exciting technologies.

-- submitted by Emily Selves