Low K dielectric

A panel of experts in the evolution of Low K dielectric spoke on Tuesday Night June 1. After a brief introduction by David McCann of Amkor Tech Ken MacWilliams of Applied Materials spoke.
Ken talked of Black Diamond (SiCOH) is now 6 years after introduction and proving its worth in manufacture. Ken stressed that the adaptation of low K has more impact on the industry than the switch to copper. However, the road to Low K has proved much more difficult than to Cu and he showed how the roadmap has been pushed out many years with the goal being K-2.9 in the next few years rather than originally thinking about approaching 1.0 at the end of the last century. One of the original problems of the film not being hard enough has been addressed so that hardness of 3GPa is achievable (SiO2 ~ 6 GPa). Because of the success of this CVD deposited film, the spin-on materials are no longer viable in Ken's mind (think SiLK). On the packaging front, Ken saw a good path to Pb-free flip-chip on organic.
Next Tom Ivers of IBM stated that classic scaling was over. Now many materials must change not just improvements in photo patterning. In particular Low-K on die was needed to get the most from either 130nm or 90nm. This need is because the passive power dissipation (conductive lines) has become equal to active power dissipation (transistors). One problem with Black diamond is the brittleness that results in cracking. It was important to limit the size of any initial crack made in processing. One way to do this was to design the edge of the die so that any cracking caused by sawing is minimized. Because of the losses in long conductive lines (1) die size is saturating despite scaling, (2) diagonal routing is being tried despite the much more complex software tools needed in design, and (3) design where most routing is in local islands of functional significance is being revisited.
K. H. Lee of TSMC next set the perspective in reminding everyone that low K was in production for 90nm at TSMC (several panel members nodded in agreement). They use the CVD low-K process. The results show a 10% power reduction compared to the same circuits in the previous best dielectric FSG (fluorinated silica glass). Like any scaling technology there were/are difficulties but none are a "wall". For example, integration with Cu was a challenge. In addition, proving reliability robustness to customers was necessary and is taking time. As an example of package reliability, some chip product of 2 cm on a side is now shipped in BGAs. Stress in vias was one hurdle for TSMC. However, he concedes that being reliable does not mean that some trade off in margins has not taken place. With each new technologies all the margins are re-optimized and the fact that one margin goes down has never meant the net result must be worse.
Mario Bolanes of Texas Instruments directly listed the challenges of this technology to TI. First the adhesion between Low-K and metals (Cu) is not as strong as Al- SiO2/N so that when their is a failure it is often at the metal to low-K interface. For example, probing tips can often damage the interface as can wire bonding which is not adjusted to the smaller windows now available. Flip-chp now often give more CTE mismatch than before. Sawing the wafers requires a more exacting process to make sure no damage is done to the edge protection. In general more moisture control is needed during processing with low-K wafers.
Ivor Barber of LSI Logic concurred with many of the points made by the IC experts but indicated that none-the-less by the end of next year LSI will only be using the Cu/Low-K fabrication for their deliverables. He did point out that the porousity of low-K has necessitated certain packaging changes on LSI's part.
David McCann indicated the packaging challenge was to develop materials / processes in packaging that can handle any Low-K solution the wafer industry sends. If separate packaging was needed for each foundry's wafers the expense would drive us back to "high-K". He summarized the low-K problems discussed by the panel:
1. Delamination under low-K because of traditional underfill. Industry must moderate the "Tg" underfill to allow a little more relaxation during temperature cycling.
2. More development of a saw process parameters and with saw blades and optimization of a good wafer seal
3. Do not require backgrinding. This is a WaterLoo for Low-K.
4. Expand wafer before die placement so you don't hit die edges when picking up another die from the tape.
5. keep metal in streets 150 microns from die corners since it gums up the saw

He summarized that Low-K is here but packaging has changed to accommodate. In bumping this means that things are moving from eutectic to high Pb bumps. Also he said don't try Pb-free and low-K in the same system. It is way to soon to make this transition.
In answer to audience questions, the panel predicted that the 65nm technology will start with the same Low-K materials and the same packaging methods perfected for 90nm. There is enormous energy behind Low-K CVD processing so it will be a while before there is another pretender to the thrown. However, cautioned against wringing our hands worrying about the lost world of robust packaging. There are inherent weaknesses in Low-K wafers but every past step of scaling presented apparent weaknesses to the packaging community and slowly they were overcome and soon just accepted as normal business and considered the new definition of "robustness."

Picture of Panel: from left, Mario Bolanes, Tom Ivers, Ivor Barber, K.H.Lee, Ken MacWilliams