Submission for CPMT Newsletter

Prepared by: Yuzo Shimada,
General Manager, Jisso and Production Technologies Research Laboratories, NEC

Submitted and edited by: Evan Davidson, IBM - Retired

 

Technical Committee on Systems Packaging (TC-14)
Erich Klink - IBM Germany, TC Chair

2004 IEEE Systems Packaging Japan Workshop

February 2 - 4; Hakone, Japan

 

The Japan Systems Packaging workshop was held this year in the beautiful mountain resort area of Hakone alongside Lake Ashinoko nearby Mount Fuji. This is the tenth Japanese workshop in a biennial string that began in 1986 as the Japan Computer Packaging Workshop held in Oiso, Japan. At its inception, the workshop encompassed all aspects of advanced electronics packaging. As time evolved more specialized packaging technology meetings began being held all over the world while important packaging applications began to broaden beyond computers and the workshop was renamed to Systems Packaging at the ninth workshop in 2002. Its new focus is on the choices, challenges, interactions and tradeoffs between all aspects of packaging technologies at the systems product level.

There were twenty-four invited presentations at this year's workshop held in seven sessions. In addition there was a most unique opportunity for all of the seventy-eight participants (sixteen from abroad) to visit the world's largest computer at the Earth Simulator Center located at the Japan Marine Sciences and Technology Center at theYokohama Institute for Earth Sciences.

Yuzo Shimada of NEC, the workshop's General Chair, gave opening remarks. His first task was to mourn the recent loss of two of the Japan committee's most active members. Prof. Koji Nihei was retired from Oki Electric and a faculty member at Waseda University. He was a former workshop chair, an IEEE Fellow and a member of CPMT's Board of Governors (BOG). Nihei-san was instrumental in building the bridges that exist today between the packaging societies in Japan and the rest of the world. He was also a renowned contributor to the semiconductor packaging industry. The other loss was Mr. John W. (Jack) Balde. Jack served as the liaison between CPMT and the Japan Systems Packaging Committee. From the beginning in 1986, Jack advised the committee and helped to organize each Japan workshop. He ran his own company (Interconnection Decisions Consulting) for over twenty years after retiring from Western Electric. He was a founding member of the Computer Society's Computer Packaging Technical Committee (now also CPMT's TC-14) in 1971 and remained actively involved with it until his death. Along the way he became an IEEE and IMAPS Fellow, a member of CPMT's BOG, and the winner of the IEEE-CPMT Millennium Medal for all of his contributions to packaging technologies and technical societies throughout the years.

The morning kick-off keynote session consisted of three speakers. Prof. Rao Tummala, past President of CPMT and Director of the Packaging Research Center at Georgia Tech, shared his vision and status of System-on-Package (SOP). He compared it with the less integrated passive component-less System-in-Package (SIP) and the earlier uses of SCMs in the '70s and MCMs in the '80s. Following this talk was one from Bob Guernsey of IBM Research and Development. He spoke about the new packaging needs and opportunities for the 45 nm silicon design node. The last morning presenter, Prof. Yoshiaki Nakano of the University of Tokyo, highlighted the recent progress that has been made in photonic networking devices and he described their recent challenges and solutions.

The afternoon session began with another keynote speech from Prof. Tetsuya Sato of the Earth Simulator Center. He described the knowledge being learned from the Simulator and its impact upon scientists throughout the world. He also talked about plans for improving the Earth Simulator to allow scientists to predict future events such as catastrophic weather phenomena with greater accuracy. Following Prof. Sato's presentation were ones from Hubert Harrer of IBM Germany, Kazunori Nakajima of Hitachi, Shinji Baba of Renesas Technology, Masateru, Koide of Fujitsu and Jun Inasaka of NEC. They gave descriptions of the packaging technologies used in IBM's z990 mainframe, Hitachi's SR11000 supercomputer, high-end flip-chip ball-grid-array substrates (FC-BGA), Fujitsu's high-end server and the Earth Simulator, respectively.

In the evening of the first day, there was a session on optical interconnections for communications systems. Takeshi Sakamoto of NTT, Takashi Mikawa of ASET and Ichiro Hatakeyama of NEC gave presentations on the subjects of packaging parallel optical interconnection modules, optoelectronic packaging technology and packaging techniques for optoelectronic interconnections, respectively. These talks were followed by a lively and interactive banquet.

At the banquet, Hisao Kanai, the 1998 workshop General Chair, reviewed the history of the Japan Computer Packaging Workshops. He also gave his views on the future of LSI packaging. After this talk, Erich Klink of IBM Böeblingen - Germany, the current TC on Systems Packaging (TCSP - TC-14) Chair, presented Yuzo Shimada of NEC, the workshop's General Chair, with a beautiful engraved wooden and brass plaque to thank him for the excellent organization work he and his team contributed to making the workshop a success. Subsequent to this ceremony, one and all enjoyed a wonderful banquet replete with great food, conversation and laughter.

The next morning Tadanori Shimoto of NEC described an ultra-thin high-density packaging technology for chip scale packages (CSP) and SIPs. Rolf Aschenbrenner of Fraunhofer IZM - Berlin illustrated the successful integration of passive and active components into organic built-up layers. A gigahertz SIP using a multi-layer thin film interposer on a silicon substrate was presented by Hirohisa Matsuki of Fujitsu. Following this, Marcos Karnezos of ChipPAC talked about 3-D packaging architectures: their design challenges and applications. To end this session, Yasuhiro Yamaji of ASET described a thermal and reliability design study for 3-D chip-stacked modules with vertical interconnections.

The afternoon of the second day was set aside for the visit to the Earth Simulator Center. During this two and half hour tour, participants were able to look at the technology and interact with the Center's experts. They saw exhibitions of the machine's capabilities and checked out the facilities and air conditioning required for cooling this massive computer. After returning to the hotel, there was a dinner party with local entertainment including "Mame-make" (throwing beans) and "Yudate-Shishimi" (a lion dance performed by a troupe from Miyagino, Hakone). Intermixed with all the fun were a myriad of technical discussions about impressions of the technical tour. (tour group in garden)

On the last day of the workshop, a morning session dealing with cellular phones and mobile information systems was held. Mitsuru Murata of NTT DoCoMo showed the latest trends in cellular handsets. Packaging solutions and system optimization for advanced wireless base-stations was described by Petri Savolainen of Nokia. This was followed by Aroon Tungare of Motorola who presented a packaging technology with embedded capacitors for cellular phones. To end this session, Tamotsu Nishino of Mitsubishi talked about suppressing multi-path coupling in a direct conversion receiver packaged on a low temperature ceramic carrier (LTCC).

Two final talks on advanced packaging were given by Osamu Okada of Casio and Eric Beyne of IMEC - Belgium. Okada-san described a wafer level chip scale package (WL-CSP) for consumer products while Beyne-san revealed a multi-layer thin film technology for systems packaging.

The 2004 Japan workshop was considered a great success by all attendees. They felt it was a great opportunity to see the most advanced work going on in all the different fields that involve semiconductor packaging. It was also a unique chance to get to know and interact with their peers from all over the world. Yuko Shimada gave the closing remarks and the next chair for the 2006 workshop was named. He will be Masakuzu Yamamoto of Hitachi.

The TC on Systems Packaging is currently planning to have a 2004 workshop in Atlanta, Georgia USA and one in Berlin Germany in 2005. The TC's web site can be checked periodically for updates. It's URL is: http://ewh.ieee.org/soc/cpmt/tc14/index.html .