3rd Asian Workshop on Signal Integrity
EDAPS 2004 -- submitted by Toshio Sudo

Electrical Design of Advanced Packaging and Systems (EDAPS) 2004
November 29, 2004 (Monday)
Clock Tower Centennial Hall, Kyoto University, Kyoto, Japan
Technically sponsored by IEEE CPMT TC on Electrical Design, Modeling and Simulation (TC-EDMS)
Sponsored by

* The 21st Century Center of Excellence (COE) Program, Kyoto University
* The Institute of Electronics, Information, and Communication Engineers (IEICE)

Objective:
The EDAPS Workshop is to enhance the technical awareness in the Asia region specifically in area of package and system electrical design concepts, issues, and challenges ahead for next generation electronic products.

Workshop Topics:

* The workshop will address the following areas:
* High-speed digital signal integrity design
* Power distribution network modeling
* RF/Microwave packaging for mobile phone
* Interconnect modeling & simulation
* EMI/EMC & electromagnetic modeling
* High-speed & high-frequency characterization
* High-density packaging; CSP, BGA, and SiP
* High-performance packaging for SOC,
* EDA tools for on-chip, package, & board design

Workshop Location:
Int'l Conf. Hall (I), Clock Tower Centennial Hall, Kyoto University Yoshida-Honmachi, Sakyo-ku, Kyoto, 606-8501, Japan

Website

https://www.kuee.kyoto-u.ac.jp/EDAPS2004/

Preliminary Program for EDAP 2004, November 29

9:00 - 9:50 Registration

9:50 - 10:00 Opening Remarks, Toshio Sudo, Toshiba Corp., Japan

10:00-10:30 Performance Prediction of On-chip Global Signaling,

Masanori Hashimoto, Akira Tsuchiya, Akinori Shinmyo, Hidetoshi Onodera, Kyoto University, Japan

10:30-11:00 Microsystem Integration: Electrical Design & Test challenges,

Mahadevan K. Iyer, IME, Singapore

11:00-11:30 Design Challenge for Mobile Platform SiP, Heeseok Lee, Package Division, Samsung Electronics, Korea

11:30-12:00 Electromagnetic Interference in a Mobile Phone, Shinji Tanabe, Mitsubishi Electric, Japan

12:00-13:15 Lunch

13:15-13:45 Fundamental Approach for 10 Gbps/pin I/O Interface System with Differential Transmission Line without Ground Plane, Kanji Otsuka and Yutaka Akiyama, Meisei University, Japan

13:45-14:15 Modeling and Simulation of High-Speed Serial Links in Complex Backplane Electrical Environments, Jared Zerbe, Rambus Inc, USA

14:15-14:45 Giga-Hertz Characteristics of Flip-chip BGA Package, Kazuyuki Nakagawa,

Renesas Technology, Japan

14:45-15:15 Spread Spectrum Clock Generator with Delay Cell Array to Reduce the EMI from a High-Speed Digital System, Jonghoon Kim, Memory Division, Samsung Electronics, Korea

15:15-15:45 Coffee break

15:45-16:15 Power Delivery Isolation Methods in Integrated Mixed Signal Systems,

Madhavan Swaminathan, Jinwoo Choi and Vinu Govind, Georgia Institute of Technology, USA

16:15-16:45 Suppression of GHz Range Power/Ground Inductive Impedance and Simultaneous Switching Noise using Embedded Film Capacitors in Multilayer Packages and PCBs, Joungho Kim, KAIST, Korea

16:45-17:15 Decoupling Simulation Method for System Electromagnetic Susceptibility

and Interconnects Modeling, Li Er Ping, Institute of High Performance Computing, Singapore

17:15-17:45 TBD

18:00-20:00 Welcome party