ISQED is the pioneer and leading international conference dealing with the design for yield, manufacturability and quality issues front-to-back. Register early to take advantage of the reduced registration fee. Please visit the web site at www.isqed.org for the advance program and registration procedure. See below for more details.
ISQED conference spans three days, Monday through Wednesday, in three parallel tracks, hosting near 100 technical presentations, six keynote speakers, two panel discussions, workshops /tutorials and other informal meetings.
ISQED 2005 offers a single full-day tutorial track focusing on a range of critical issues in circuit design and packaging at sub-90nm CMOS. We are pleased to have several noted experts in their respective fields (Design methodologies for implementing robust circuits with desired power performance characteristics, Managing leakage power, Circuit Design in the Presence of Uncertainty, and Modeling and Design of Chip-Package Interface) to present the latest research in these compelling areas as follows:
Design of sub-90nm Circuits and Design Methodologies Ruchir Puri, IBM TJ Watson Research Center, NY Sachin Sapatnaker, Electrical & Computer Engineering, University of Minnesota Tanay Karnik, Intel Circuit Research Labs, Hillsboro, OR Rajiv Joshi, IBM T J Watson Research Center, NY
Modeling and Design of Chip-Package Interface Luca Daniel, Massachusetts Institute of Technology, Cambridge, MA Byron Krauter, IBM Microelectronics, Austin, TX Lei He, UCLA EE Dept, Los Angeles, CA
John Kibarian, President & CEO, PDF Solutions Ashok K. Sinha, Sr. VP & GM, Applied Materials Joe Sawicki, Vice President & General Manager, Mentor Graphics Aki Fujimura, Chief Technology Officer, Cadence Design Systems Kurt A. Wolf, Director, Library Management Division, TSMC Bernard Candaele, Department Head, SoC, IC & EDA, Thales, Paris , France
ISQED is pleased to offer two high-power evening panel discussion sessions, where many leading experts, address the important issue of quality design. These panels would focus on the following topics:
1 IP Creation and Use
What roadblocks are ahead or it is just clear and bumpy road?
2 Nanoelectronics: Evolution or Revolution?
IP Quality: A Design, not a Verification Problem Michael Keating, Synopsys
ISQED Technical sessions start on Tuesday March 22, and continue until the afternoon of Wednesday, March 23. Beside the above plenary sessions, panel discussions, and workshops, the program consists of nineteen technical sessions featuring near 100 papers on various challenging topics related to design for manufacturability and quality. A list of topics includes:
- EDA Tools & IP Blocks; Interoperability and Implications
- Design for Manufacturability & Quality (DFMQ)
- Design Verification and Design for Testability (DVFT)
- Package - IC Design Interactions & Co-Design (PDI)
- Robust Device, Interconnect, and Circuits (RDIC)
- Physical Design, Methodologies & Tools (PDM)
- Effects of Technology on IC Design, Performance, Reliability, and Yield
- System Level Design, Methodologies and Tools (SDM)
Please refer to ISQED web site at www.isqed.org for information regarding the tutorials, conference, tutorials, and hotel registration. Early registration is recommended to take advantage of the discounted registration fee.