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I-V Maps

Robert B. Darling, Senior Member, IEEE


Abstract - A graphical circuit mapping technique is introduced for purposes of visualization and instruction. The technique is oriented toward mainly planar circuits which operate from fixed power supply rail voltages, and which are typical of most integrated circuit designs. The I-V map allows a simultaneous representation of all voltages, currents, and power dissipations, and can be constructed to scale, which then gives accurate magnitude information. The I-V map proves valuable to recognizing current and voltage distributions, elements of high power dissipation, and as a classroom instructional tool for Kirchhoff's laws.


I. Introduction

Conventional circuit diagrams or schematics emphasize the interconnections between elements and thus give the most direct representation of a circuit, particularly when viewed as a set of construction specifications. However, a conventional schematic only illustrates the actual operating state of the circuit when it is annotated with particular values for voltages or currents. The relationships between these currents and voltages are nevertheless the most important aspect for the objective of purposeful design, and these relationships are only minimally represented even with directed graphs of the circuit topology.

The successful design and understanding of electronic circuits makes better use of an abstract variable space which is not directly represented on a conventional schematic, but which is tacitly used by nearly all who routinely perform circuit design or analysis. Often, fluency with this abstract variable space is termed having a good "intuitive feel" for the subject. Indeed, instructors usually associate a student's grasp of this abstract space as a measure of her or his understanding of circuit theory. Yet students are often left to their own resources to acquire this necessary "intuition."

The purpose of this article is to illustrate a graphical mapping technique which formalizes this abstract space in a manner in which precise, quantitative methods can be applied, which provides a concrete workspace for which to display precisely what this so-called circuit design intuition is, and which also allows for strong visualization of the circuit variable relationships which are not normally expressed in a conventional schematic or directed circuit graph. The technique is termed I-V mapping and is based upon the principles of power flow through supply and dissipative elements and upon geometric representations of Kirchhoff's laws.


II. Domain of the Map

The technique of an I-V map is derived from some natural tendencies and common practices used in the schematic layout of practical circuits. Circuit nodes are most commonly arranged on the page with higher voltages toward the top, so that positive current flows downward on the page through the dissipative elements. Power supply rails are commonly drawn as horizontal lines extending across the page, which then supply current to any devices providing a path to another rail voltage. The power supply voltage sources are usually suppressed from the schematic for brevity, since the interest is normally focused upon the dissipative elements which are driven by these voltage sources.

These same features are carried over and formalized in an I-V map. The domain of an I-V map is a 2-dimensional space with a horizontal axis of current and a vertical axis of voltage. The concept of an I-V map builds upon a hydrodynamic analog to electric current flow, in which a sheet of current flows from an upper power supply rail to a lower one. The current sheet is given a constant current density per unit width of the page so that current flows can be measured horizontally in much the same manner as potential differences being measured vertically when a constant voltage gradient per unit length of the page is imposed. Forcing both axes of the map to behave linearly with voltage and current imparts a quantitative as well as qualitative value to the I-V map.


III. Elements and Properties

Each circuit element is represented on an I-V map by a particular enclosed area. A resistor, or any other two-terminal element is represented as a simple rectangle, as shown in Fig. 1.

Figure 1. I-V map for a resistor or other two-terminal element.

Figure 1. I-V map for a resistor or other two-terminal element.

The vertical height of the resistor is proportional to the voltage V across it, and the horizontal width is proportional to the current I flowing through it. It is important to note that this representation of the resistor provides two other valuable pieces of information which can be obtained by inspection. The value of the resistor, i.e., its resistance, is the aspect ratio of the rectangle, R = V/I, and the power dissipation of the resistor is equal to the enclosed area, P = IV. Small valued resistors are short and fat, while large valued resistors are tall and skinny. Since the area of such a rectangle must be non-negative, only power dissipative elements appear on an I-V map. Thus, elements such as DC power supplies cannot be represented directly on the I-V map, but in most cases the primary interest lies with the elements which are driven by these sources. For similar reasons of brevity, power supplies are normally omitted from electronic schematics, or abstracted into a background issue. As will be discussed later in Sec. VI, the elements which supply power can be treated through a simple extension of the I-V map.

Different circuit elements are placed adjacent to one another on an I-V map in a manner which corresponds to their circuit interconnections. One accomplishes this by visualizing a current flow which is downward on the page, entering each enclosed area on the topmost boundary (the top of each rectangle for a resistor) and exiting at the bottom boundary of each enclosed area (the bottom of each rectangle for a resistor). If two elements are placed in series, they must have the same current flow, and they consequently have the same dimensional width. If two elements are placed in parallel, they must have the same terminal voltage, and they must consequently have the same dimensional height. Voltage division and current division are then represented by simply the relative manner in which a vertical or horizontal distance is divided up among the elements which share the interconnection. In this way, Kirchhoff's voltage and current laws (KVL and KCL) are explicitly enforced for a planar network by arranging the enclosed areas such that no space is left blank and no two enclosed areas are overlapping. In other words, the individual elements must fully tile the available area of the map. The dual of a given network can be constructed by simply interchanging the voltage and current axes of the I-V map, or equivalently, by flipping the I-V map about its I = V diagonal.

Figure 2. Bridge circuit and its I-V map. (a) Circuit, (b) unbalanced, and (c) balanced.

Figure 2. Bridge circuit and its I-V map. (a) Circuit, (b) unbalanced, and (c) balanced.

Figure 2(a) shows an H-network or bridge circuit which illustrates these ideas. The two power supply voltages bound the I-V map at top and bottom, and the overall width of the I-V map gives the total current drawn from the power supply rails. Since each element of the circuit is purely power dissipative, the overall I-V map forms a rectangle whose area gives the net power dissipation for the circuit, as in Fig. 2(b). This particular bridge is drawn as unbalanced, so that a net current flows through R3 from right to left. This requires that the node voltage between {R1,R2,R3} to be lower than the node voltage between {R3,R4,R5}, as shown in the I-V map. Similarly the current flow through R3 steals current from R4 and delivers it to R2, which is also indicated in the I-V map. As the bridge becomes more balanced, the current through and the voltage across R3 are reduced to zero, giving the I-V map of Fig. 2(c). This provides a simple geometric illustration of the necessary condition for balancing the bridge, namely that R1R5 = R2R4. Notice that a two-terminal element with I = V = 0 vanishes on the I-V map, as in the case of R3.

Figure 3. (a)Bipolar junction transistor, (b) I-V map for forward active, and (c) I-V map for saturated operation.

Figure 3. (a)Bipolar junction transistor, (b) I-V map for forward active, and (c) I-V map for saturated operation.

A three-terminal device, such as a bipolar junction transistor, has the I-V map illustrated in Fig. 3. Since a three-terminal device is a 2-port network, each port produces a rectangle on the I-V map. The I-V map of Fig. 3 illustrates the ordering of the terminal voltages and the manner in which the base and collector current sum to yield the emitter current for both forward active (Fig. 3(b)) and saturated (Fig. 3(c)) operation. Since the power dissipation of the BJT is PT = VbeIb + VceIc, each of the contributing rectangles explicitly shows the power dissipated by the base and collector ports.


IV. Further Examples

The flow of bias currents and the node voltage ordering of bias circuits is also particularly well illustrated by an I-V map. Figure 4 shows the case for a single BJT and the manner in which the base current affects the division of voltages at the base node.

Figure 4. Single transistor biasing andits I-V map.

Figure 4. Single transistor biasing and its I-V map.

Again it should be noted that the overall I-V map forms a rectangle, since all of the constituent devices are power dissipative, and no current enters or leaves the circuit other than through the power supply rails. Figure 5 shows a simple BJT differential pair working from a current source. The I-V map readily shows which devices are the principal ones for power dissipation, without requiring any extensive calculations. Furthermore, the relative imbalance between the two transistors of a current source is also readily evident.

Figure 5. Bipolar transistor differential pair and its I-V map.

Figure 5. Bipolar transistor differential pair and its I-V map.

I-V maps are also useful for circuits which involve directing large current flows, such as in high-current power amplifiers. The I-V map for a complementary output stage is shown in Fig. 6.

Figure 6. Complementary output stage and its I-V map for a positive output voltage.

Figure 6. Complementary output stage and its I-V map for a positive output voltage.

In this instance, the case of a positive output voltage is represented. Here, the I-V map gives an instantaneous snap-shot of the state of affairs within the circuit which is not restricted to only bias conditions. Figure 6 also illustrates how additional power supply rails (such as a bipolar or dual power supply) can be included, as well as how currents entering or exiting the circuit through leads other than the power supply rails can be taken into account, such as with the grounded load resistance which is illustrated. Once more, only those elements through which current is flowing appear on the I-V map. In the case of Fig. 6, transistor Q6 of the class-B output stage and overcurrent protection transistors Q8 and Q9 do not appear on the I-V map since they are not active in the circuit for the case of an in-range positive output voltage.

A similar example of more complex power flows is provided by the positive, series-pass voltage regulator, shown in Fig. 7. This depiction of the voltage regulator allows a very clear visualization of its power conversion efficiency and how this is determined by its topology and element bias points.

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Figure 7.  Positive, series-pass voltage regulator and its I-V map.


V. Reactive Elements

Only elements which are dissipating power appear on the I-V map, and reactive elements can be so represented, but only for the duration over which they are absorbing energy.  In DC steady-state, reactive elements will have fully charged, and will not appear on the I-V map, but during a transient, the I-V map can provide useful visualization of the behavior of reactive elements. The response of a series R-C and R-L network to an applied voltage step are shown in Fig. 8. As time increases, the capacitor charges up to the applied voltage step height, by which point the current in the circuit ultimately falls to zero. Figure 8(a) shows the I-V maps for snap shots along this exponential charging transient. Similarly, as time increases, the inductor flux accumulates in proportion to the current flow, with the inductor voltage ultimately falling to zero, as shown in Fig. 8(b). While the exponential time dependence is not evident from the I-V map, the restrictions imposed by Kirchhoff's laws and the initial and asymptotic states of the transient are easily visualized.

tedu1f8.gif (14100 bytes)

Figure 8. Reactive elements and their I-V maps in response to a voltage step.  (a) Series R-C circuit.  (b) Series R-L circuit.


VI. The Power Supply Layer

Elements which supply power to the circuit would have a negative area and thus cannot be directly represented on the I-V map. This includes both DC power supplies and reactive elements during intervals over which they are supplying power. This limitation can be overcome by the introduction of a power supply layer which complements the existing power dissipation layer of the I-V map.

Since the power delivered to the dissipative elements of the circuit must precisely balance the power produced by the supply elements, for each I-V map of the dissipative elements there must exist a complementary I-V map of the supply elements.  Further, the size and shape of the supply and dissipation I-V maps must be exactly the same. This concept can be visualized as a supply layer and a dissipation layer which lie over top of each other.  The supply and dissipation I-V maps have exactly the same outline, although each is internally comprised of different circuit elements. Current flows from the top edges of the supply layer into the top edges of the dissipation layer, and vice-versa on the bottom edges to preserve continuity. The development of the power supply layer is illustrated in Fig. 9.

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Figure 9. Development of the power supply layer.

For simple DC bias situations, as have been previously discussed, the power supply layer is normally of little interest, following the common practice of omiting the power supplies in circuit schematics. However, more complex power exchange occurs when a reactive or other energy storage element is present. This situation is shown in Fig. 10 and illustrates how the power supply layer can provide useful insight as the power production or dissipation of an element changes with varying circuit conditions. A voltage step is initially applied to the circuit of Fig. 10(a), and thereafter capacitor C1 begins charging upwards, illustrated in the I-V map of Fig. 10(b). Ultimately C1 charges to a voltage of V1*R1/(R1 + R2), as shown in Fig. 10(c). At this point no more power is dissipated within C1 and it vanishes from the dissipation I-V map. Next, the voltage source V1 is abruptly lowered, and C1 now delivers power back into the remaining circuit elements as it begins to discharge through R1. During the course of these events, C1 dissappears from the dissipation layer and now reappears in the supply layer. As the voltage source V1 amplitude falls further, it will soon fall below the instantaneous voltage across C1. When this occurs, current will flow back into the voltage source V1, as supplied by the discharge of capacitor C1. In this case, the voltage source V1 makes a transition from the power supply layer to the dissipation layer.

In this manner, energy storage effects can be represented and illustrated by the I-V mapping technique. The complementary nature of the supply and dissipation layers of the I-V map help to illustrate the conservation of power flow within the system. Precisely equal sizes and shapes of the supply and dissipation layers provides a thorough validation of an existing circuit analysis based upon energy conservation principles.

tedu1f10.gif (15982 bytes)

Figure 10. Energy storage effects represented on an I-V map.  (a) Circuit.   Supply and dissipation layers:  (b) while C1 is charging up; (c) after C1 has fully charged; (d) after V1 has abruptly fallen below its original value, and (e) after V1 has fallen below the instantaneous voltage stored on C1.


VII. Application of I-V Maps

The I-V mapping technique is not a method for circuit analysis or synthesis, but rather a visualization tool which can be helpful in either. The unique feature of the I-V map is that it simultaneously provides a graphical representation of a circuit's topology and operating state within the same diagram. Power flow and Kirchhoff's laws are geometrically represented within the I-V map, and this enables the I-V map to become a useful tool for visualization of circuit topology and element relationships, and for validation of an existing analysis or design. Violations in power flow conservation or Kirchhoff's laws would become immediately apparent as the element blocks would no longer tile the overall area of the supply and dissipation maps. Because the I-V map is developed from concepts of power flow conservation, it can be easily used to verify power requirements of a circuit, identify thermal problems, visualize signal swings, and maximum voltage and current conditions on individual components. Graphical or geometrical features often prove more visually striking in problem identification than do raw numerical data.

The technique of I-V mapping has been introduced to senior electrical engineering students in several electronic circuit design classes at the University of Washington. The technique has been found to have good instructional value, particularly in helping students check their solutions to analysis problems and in helping students to grasp the relationships between currents and voltages that are imposed by a given circuit topology. Several students have extended the technique to mapping entire operational amplifiers, voltage regulators, and power amplifiers. These complete maps provide at-a-glance information on which devices and subcircuits are dissipating high voltages, current, or power, and this information can then be directly used in managing thermal effects for layout purposes. It is possible that this mapping technique could also provide a convenient post-processor for computer-aided circuit simulators, such as SPICE or SABER.


VIII. Conclusions

A graphical mapping technique has been presented which illustrates the instantaneous state of a planar circuit. This representation of the circuit state allows easy verification of Kirchhoff's laws, easily illustrates the various distribution of voltages and currents throughout the circuit, and when performed on scaled axes can give a rapid assessment of the principal power dissipating elements with minimal required calculations. Reactive elements and energy storage effects can be represented through the use of a complementary supply and dissipation I-V map. The I-V mapping technique is most suitable for circuits used in integrated electronics, such as operational amplifiers, logic gates, voltage regulators, and power amplifiers. The use of this technique in senior-level electronics classes has had positive effect on the student's ability to grasp the "intuition" part of circuit analysis and design, making the I-V map is a useful tool for visualization or validation of electronic circuits.


Acknowledgements

The author wishes to thank Prof. Jonny Andersen for helpful discussions and the students of EE-433 for enduring the early development of these ideas.


Author Contact Information

Robert B. Darling http://www.ee.washington.edu/faculty/darling.html
Department of Electrical Engineering, Box 352500
University of Washington
Seattle, WA 98195-2500
Phone: (206) 543-4703
Fax: (206) 543-3842
E-mail: bdarling@ee.washington.edu


Author Biography

Robert B. Darling (Sí78-Mí86-SMí94) was born in Johnson City, TN on March 15, 1958. He received the B.S.E.E. (with highest honors), M.S.E.E., and Ph.D. degrees in Electrical Engineering from the Georgia Institute of Technology in 1980, 1982, and 1985, respectively.

He has held Summer positions with Sperry-Univac, Bristol, TN, and Texas Instruments, Johnson City, TN, and from 1982 to 1983, he was with the Physical Sciences Division of the Georgia Tech Research Institute, Atlanta, GA. In 1985, he joined the Department of Electrical Engineering, University of Washington, Seattle, as an Assistant Professor. He was promoted to Associate Professor in 1990, and to Full Professor in 1999. From 1995 to 1996, he was a Visiting Associate Professor at Stanford University, Stanford, CA. His research interests include electron device physics, device modeling, microfabrication, circuit design, optoelectronics, sensors, electrochemistry, and instrumentation electronics.

Dr. Darling is a member of the American Physical Society, the American Vacuum Society, the Optical Society of America, and is a registered professional engineer in the State of Washington.


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