N4B4  Trigger and Front-End Systems

Thursday, Nov. 5  10:30-12:10  Pacific Salon 3

Session Chair:  Craig Buttar, University of Glasgow, United Kingdom; Ryosuke Itoh, KEK, Japan

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(10:30) N4B4-1, Pulsar IIb Design, System Integration and Next-Generation Full Mesh ATCA Backplane Test Results

Z. Xu1, Z. Hu2, J. Olsen2, T. T. Liu2

1Dept. of Physics, Peking University, Beijing, China
2Particle Physics Division, Fermilab, Batavia, IL, USA
The Pulsar IIb is a custom ATCA full mesh enabled FPGA-based processor board which has been designed with the goal of creating a scalable architecture abundant in flexible, non-blocking, high bandwidth interconnections. The design has been motivated by silicon-based tracking trigger needs for LHC experiments. In this talk we describe the Pulsar II hardware, our full-crate integration tests, the results of our 40G and 100G ATCA full mesh backplane performance tests, and the experience gained throughout this process.

(10:50) N4B4-2, Trigger Architecture of the Supernemo Experiment

O. Duarte

SERDI, CNRS / IN2P3 Laboratoire de l'accelerateur Lineaire, Orsay Cedex, France

On behalf of the LAL SuperNEMO group
SuperNEMO (SN) is the next-generation (0?ßß) experiment based on a tracking plus calorimetry technique. The construction of the demonstrator has started in 2012 and its installation is expected in 2015 in LSM underground laboratory (France). The SN experiment is designed to measure both energy and time of flight of each beta particle emitted from ßß decays. The demonstrator is made of a calorimeter (712 channels) and a tracking detector (6102 channels). These detectors front-end electronics use an unified architecture based on six similar crates that each host up to 20 Front-End Boards (FEB) and one SN_CROB board. Moreover a Trigger Board SN_TB is plugged in one of the remaining empty slot of a calorimeter crate. The FEBs perform the acquisition of the detector channels. The SN_CROB board gathers the front-end data from the calorimeter or tracker FEBs and sends them through Ethernet link to the data acquisition (DAQ) system. It extracts the Trigger Primitive (TP) from the front-end data and sends them through serial link to the Trigger Board (SN_TB). At each clock tick (25ns), we collect TP signals associated to each tracker and calorimeter channels. The trigger system is designed to merge all these TP signals and make a decision from these informations within a central programmable SN_TB. The trigger system has several relevant part: The calorimeter integrates 2 trigger thresholds: a major high energy threshold and a low energy threshold in order to detect low energy particles. The tracker provides the possibility of a second triggering for a delayed particle. The calorimeter or tracker part of the trigger system can operate separately. We have an overlap between the zoning of the calorimeter and the tracker. That means, the final trigger decision is made considering spatial coincidences between hits from the calorimeter and tracker detectors.

(11:10) N4B4-3, POLAR Trigger - Experimental Verification

R. M. Marcinkowski

Proton Irradiation Facility, Paul Scherrer Institute, Villigen, Switzerland

On behalf of the Polar Collaboration
POLAR is a space instrument designed for measurements of the polarization of the X-rays from the GRBs. It is developed by the European-Chinese collaboration and will be launched on-board of the Chinese SpaceLab TG-2. GRBs are short flashes of X-rays. Measurement of polarization of X-rays comes down to search of, at least two, coincident energy depositions of Compton scattered photon. Instruments devoted to measure polarization are usually built with segmented detectors and electronics that plays role of coincident system. Measurement of Polarization in POLAR bases on scattering of X-rays between two scintillation bars. The array of 1600 bars is read by 25 Modules. Modules are controlled by Central Processing Unit (CT). The impact of Polar scientific results strongly depends of the effective of triggering mechanism of event selection on-board. Each Module looks for energy depositions in each channel and generates 3 digital trigger signals corresponding to: deposition in 1 bar, deposition in 2 bars and many depositions. CT analysis these signals and decides about acceptance of the event. CT accepts events if * at least 2 channels in 1 Module are fired, * at least 2 Modules show single deposition. Verification of the triggering concept and its implementation in Polar was split over many stages of tests. They used: * Internal Pulsers - subsystems of each Module that can mimic signal from 1 channel and were used to test every Polar Module during production, * External Pulsers - device attached to Module that produce any signal pattern (single or multiple event). External Pulsers were used to test Trigger of each Module as well as to test fully assembled Polar, * Radioactive Sources, X-Ray Fluorescence Sources and Synchrotron Beams. Trigger was deeply tested for various event rates and trigger patterns. Acceptance and rejecting algorithms have been successfully verified. Polar Team is preparing the instrument for test on the beam at ESRF in Grenoble, now.

(11:30) N4B4-4, Characterization of the 8-Channel Single-Photon Counting Front-End Chip for the Upgrade of the LHCb RICH Detectors

M. Fiorini1, M. Andreotti1, W. Baldini1, M. Baszczyk2, R. Calabrese1, A. Candelori3, P. Carniti4, L. Cassina4, A. Cotta Ramusino1, P. Dorosz2, A. Giachero4, C. Gotti4, W. Kucewicz2, E. Luppi1, M. Maino3, R. Malaguti1, A. Matalon1,5, L. Pappalardo1, G. Pessina3, L. Tomassetti1

1Universita' degli Studi di Ferrara and INFN Sezione di Ferrara, Ferrara, Italy
2AGH-University of Science and Technology and INP, Krakow, Poland
3Sezione di Padova, INFN, Padova, Italy
4Universita' degli Studi di Milano Bicocca and INFN Sezione di Milano Bicocca, Milan, Italy
5University of Chicago, Chicago, USA
A 8-channel fast single-photon counting front-end ASIC has been designed in 0.35 micron CMOS technology for the upgrade of the LHCb RICH detectors at CERN. The chip allows fast photon counting up to 40 MHz, with a peaking time of 5 ns and a power consumption of about 1 mW per channel. Results on the characterization of the first version of the chip are presented, including measurements in the lab with a dedicated test system. Radiation hardness tests are described as well, including measurements of total-ionizing dose and single event effects.

(11:50) N4B4-5, The FTK to Level-2 Interface Card (FLIC) for the ATLAS Experiment

J. Anderson, B. Auerbach, R. Blair, G. Drake, A. Kreps, J. Love, J. Proudfoot, R. Wang, J. Zhang

Argonne National Lab, Argonne,IL, USA
The FTK to Level-2 Interface Card (FLIC) is the final component of the ATLAS Fast TracKer (FTK), a custom electronics system for the ATLAS trigger upgrade. The FTK performs full event tracking using the ATLAS Silicon detectors for every Level-1 accepted event at 100 kHz. The FLIC is a custom Advanced Telecommunications Architecture (ATCA) card that interfaces the upstream FTK system with the ATLAS trigger and data acquisition (TDAQ) system, and allows for event processing on commercial PC blades making use of the 10 GB Ethernet full mesh ATCA back-plane. The FLIC receives data on 8 optical links at a bandwidth of ~1 Gbps per channel, reformats the data to the ATLAS standard record format, and performs the conversion from local to global module identifier using look up tables in SRAM. After processing, the event records are sent out to the TDAQ system using the S-LINK protocol at 2 Gbps, with a latency of O(10) microseconds. The data processing is handled in two Xilinx Virtex-6 FPGAs, with two additional Virtex-6 FPGAs communicating with the processor blades over the ATCA back plane. The four FPGAs are connected via a full internal mesh of high speed GTX lines. This paper reports design goals, implementation and testing results of the FLIC.