N4C2  Front-Ends Circuits

Thursday, Nov. 5  14:00-16:00  San Diego

Session Chair:  Angelo Rivetti, Istituto Nazionale di Fisica Nucleare - INFN - Sezione di Torino, Italy; Jan Kaplon, CERN, Switzerland

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(14:00) N4C2-1, Experimental qualification of an 8-channel selectable-gain CMOS frontend for Double-Sided Silicon Strip Detectors

A. Castoldi1,2, C. Guazzoni1,2, T. Parsani1,2

1Dip. Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italy
2Sezione di Milano, INFN, Milano, Italy

We are currently developing a modular Femtoscope ARray for Correlation and Spectroscopy, named FARCOS, featuring high angular and energy resolution and able to address several open cases in nuclear physics. The detection system is arranged in a modular assembly of telescopes. Each telescope features an active area of 6.4 × 6.4 cm2 and is composed of three detection stages. 300 µm thick and 1500 µm thick 32 x 32DC-coupled Double-Sided Silicon Strip Detectors (DSSSDs) provide the two ?E stages. The third stage is composed of four CsI(Tl) crystals with an active area of 3.2 × 3.2 cm2 and an absorption length of 6 cm. A peculiar feature of FARCOS is the identification of fragments stopping in the first detection layer via pulse-shape analysis. This contribution is devoted to the design and experimental qualification of a multi-channel double-polarity selectable-gain CMOS frontend in 0.35µm CMOS AMS technology to be coupled to the FARCOS silicon layers. The frontend comprises the charge preamplifier, an output stage to drive the connection to the line drivers and some additional slow-control circuitry. To comply with the different foreseen experimental scenarios we implemented a selectable-gain strategy with a wide variety of dynamic ranges – 90 MeV, 200 MeV, 350 MeV and 500 MeV. For ease of operation and fault replacement, the same ASIC design reads out both the junction-side strips and the ohmic-side strips. The presentation will focus on the relevant design issues and on the full experimental characterization of the first and second version of the chip with an eye on the comparison with the post-layout simulations. In addition we will present the performance of the chip coupled to the DSSSDs.

(14:20) N4C2-2, Optimized Front-End Electronics and Digital Signal Processing for Recently Developed Scintillators

S. Riboldi1,2, A. Giaz2, S. Brambilla2, F. Camera1,2, C. Boiano2

1Physics Dept., Universita' degli Studi di Milano, Milano, Italy
2Milano Sect., I.N.F.N., Milano, Italy

The recently developed scintillator crystals (e.g. LaBr3:Ce, CLYC) offer significant improvement in energy resolution (e.g. below 3% for LaBr3:Ce at 662 keV) but requires a more careful approach in the design of the analog front-end and processing electronics, in order to fully exploit the intrinsic potentiality of the detectors. Moreover, the CLYC scintillators can be used for spectroscopy of both gamma rays and fast and thermal neutrons, providing different scintillation light time decays that allow to identify the two different interactions by means of pulse shape discrimination techniques. Pulse shape analysis is also required by phoswich detectors, composed by two different, optically coupled scintillators and a single photo-multiplier tube, in order to disentangle the energy contributions deposited in either section of the detector (e.g. LaBr3 and NaI in case of the PARIS phoswich detector). In this work, we first propose a simple improvement in the analog front-end electronics, that allows to simultaneously better exploit the intrinsic potentiality of CLYC crystals in terms of energy, time resolution and pulse shape discrimination, using a less demanding analog to digital converter. Moreover, the DPLMS method for optimum filter synthesis, slightly modified in order to cope also with the time correlated, scintillation generation noise, will be used to calculate digital filters for energy and pulse shape discrimination for LaBr3 and CLYC scintillators. The performance of the optimum filters matched to the real experimental noise conditions will be compared with the performance of a few traditional and commonly used filters (e.g. moving window, trapezoidal, matched filter, etc.), for various experimental set-up of front-end electronics (with or without charge sensitive preamplifier), scintillators and phototubes, showing the effectiveness of the noise matched optimum filters with respect to the generic ones.

(14:40) N4C2-3, Double Slope Dynamic Range Enhanced Charge Sensitive Amplifier

E. Bechetoille, H. Mathez

IPNL CNRS/IN2P3 MICRHAU, Villeurbanne, FRANCE

A cryogenic and low noise front end ASIC has been developed for WA105 experiment. Considering previous designs, the dynamic range had been multiplied by 6. In order to absorb high input charge and maintain low noise for small signals, we converged to a double slope functionality. The identical channel of this 16-channel chip is made of a low noise Charge Sensitive Amplifier (CSA) with a MOSCAP around 500fF and a 2MO feedback resistor. The CSA is followed by a line driver. The input referred noise level requires at least 1500 e- rms at -160°C with an input detector capacitance (Cdet) of 250pF. With such performance, the input signal range of 3fC to 1.2pC is attainable. This front end is implemented in standard 350nm CMOS process.

(15:00) N4C2-4, Performance of the New Amplifier-Shaper-Discriminator Chip for the ATLAS MDT Chambers at the HL-LHC

H. Kroha1, S. Abovyan1, V. Danielyan1, M. Fras1, F. Mueller1, S. Nowak1, R. Richter1, K. Schmidt-Sommerfeld1, Y. Zhao1, A. Baschirotto2, F. Resta2, M. De Matteis2

1Max-Planck-Institut fuer Physik, Munich, Germany
2Physics Department, University of Milano-Bicocca, Milano, Italy

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discri¬mi¬na¬tor (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

(15:20) N4C2-5, System Architecture of a Fully Combined PET/CT Scanner using LabPET(TM) Electronics with an Upgraded Analog Front-end Optimized for PET and CT Counting Mode Operation

M. S. Traore1, C. Thibaudeau1,2, K. Koua1, M.-A. Tetrault1, C. M. Pepin2, J. Cadorette2, J.-F. Pratte1, R. Lecomte2, R. Fontaine1

1Universite de Sherbrooke, Institut Interdisciplinaire d'Innovation Technologique (3IT), Sherbrooke, Quebec, Canada
2Universite de Sherbrooke, Sherbrooke Molecular Imaging Center, Department of Nuclear Medicine and Radiobiology, Sherbrooke, Quebec, Canada

High light yield lutetium based crystals, such as LYSO, enable new potentials in medium and low energy radiation detection. Such scintillators combined with high quantum efficiency avalanche photodiodes (APD), have shown promising results for fully integrated PET/CT scanners. In such systems, a single detection apparatus is used for the acquisition of both PET and CT signals, allowing reduced hardware and potentially lower effective scanner cost. Using this approach, a prototype PET/CT scanner is developed using the LabPE(TM) digital electronics and a new upgraded front-end analog board optimized for PET and CT operation. The upgraded analog board has 2 x 64 acquisition channels based on LYSO crystal arrays (pixel size of 1.125 x 1.125 x 12 mm3) coupled 1:1 to pixelated APD photodetectors. The analog signal outputs are amplified by an optimized application-specific integrated circuit (ASIC) that offers dual charge sensitive pre-amplifier (CSP) and shaper gain modes for individual channels. For PET acquisition, the CSP-Shaper gain is adjustable from 8 to 48 mV/fC, while CT acquisition can operate from 65 to 390 mV/fC. Moreover, the LabPET firmware was updated and optimized to meet the new hardware requirements. This paper describes the architecture of the prototype PET/CT scanner and focuses on the effect of these updates on the counting performance for both PET and CT acquisition modes. In PET operation, the events processing rate has shown a 15% improvement compared to the previous firmware version. Each channel has reached an average count rate of ~17 500 cps (counts per second). In CT mode, the firmware recorded a maximum average count rate of 400 000 cps per channel, thus allowing a total of ~25 million cps considering all 64 channels of one LabPET digital board.

(15:40) N4C2-6, An Asynchronous Front-End Channel for Pixel Detectors at the HL-LHC Experiment Upgrades

L. Ratti1,2, F. De Canio3,2, L. Gaioni3, M. Manghisoni3,2, V. Re3,2, G. Traversi3,2

1Electrical, Computer and Biomedical Engineering, University of Pavia, Pavia, Italy
2INFN, Pavia, Italy
3Engineering and Applied Sciences, University of Bergamo, Dalmine, Italy

Pixel detectors to be assembled for the upgrades of the HL-LHC experiments will be confronted with new challenges in terms of radiation tolerance, hit rate, power density and space resolution. This paper is concerned with the experimental characterization of a front-end channel prototype for pixel detectors based on a Krummenacher network to continuously reset the charge sensitive amplifier and implementing a time-over-threshold (ToT) method to perform amplitude measurement. The circuit was developed in a 65 nm CMOS technology and takes an overall area not exceeding 25 um 50 um. The power dissipation per channel, not including dynamic consumption, is around 5 uW. Noise at the nominal detector capacitance of 100 fF is slightly larger than 110 electrons. The paper will also discuss the radiation tolerance features of the front-end channel, which will be exposed to up to 10 MGy of total ionising dose to emulate the system operation in the actual experiment.