N3C3  Semiconductor Detectors 2

Wednesday, Nov. 4  14:00-16:00  Golden West

Session Chair:  Cinzia DaVia, University of Manchester, ; Andrea Castoldi, Politecnico di Milano and INFN, Italy

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(14:00) N3C3-1, HVCMOS Pixel Detectors - Recent Results and New Designs

I. Peric, F. Ehrler, R. Blanco, R. Leys

IPE, KIT, Karlsruhe, Germany
High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland) and are considered as an option for ATLAS strip and pixel layers (LHC/CERN) and CLIC (CERN). The Mu3e detector will be 50 micrometers thin detector with an area of 2 square meters. For CLIC a capacitively coupled hybrid pixel detector is proposed, where the capacitive signal transmission is used for the readout of sensor signals. For ATLAS there are several detector options including hybrid and monolithic sensors – the total area of the sensor will be nearly 100 square meters. We will focus on the experimental results obtained with the capacitively coupled and monolithic sensors and describe the new designs.

(14:20) N3C3-2, Charge Collection Studies in HVCMOS Sensors

G. Kramberger

Jozef Stefan Institute, Ljubljana, Slovenia
The charge collection mechanism in HVCMOS sensors produced by AMS was studied by Edge-TCT and by measuring signals from minimum ionizing particles before and after neutron irradiations. The drift component of the induced current was found to increase with irradiation while the diffusion one was diminishing. Such behavior was attributed to the initial acceptor removal on one side and reduction of minority carrier lifetime on the other. Reduction of Neff results in wider depleted region and therefore charge collection efficiency for heavily irradiated sensors can remain very high even for short shaping times at moderate bias voltages. A very good agreement between both measurement techniques was observed.

(14:40) N3C3-3, High Speed X-Ray Imaging and Spectroscopy with Novel Direct Detection CMOS Based Active Pixel Sensors

S. Aschauer1, G. Lutz1, P. Majewski1, M. Porro2, L. Strüder1,3

1PNSensor GmbH, Munich, Deutschland
2Max Planck Institute for extraterrestrial Physics, Munich, Deutschland
3University of Siegen, Siegen, Deutschland
Since many years DEPFETs have been developed for space and ground based X-ray imaging and spectroscopy experiments. A DEPFET is an integrated detector amplifier combining internal amplification, full sensitivity over the whole bulk thickness, analog data storage, readout on demand, low serial noise and absence of reset noise. Over the past years, the DEPFET technology was improved and additional features of DEPFETs were developed: increase of dynamic range, improvement of radiation hardness, implementation of electronic shutters, integration of an analog storage, reduction of readout noise and improvement of the low energy performance. This presentation will show the high-speed spectroscopy and imaging capabilities of existing DEPFET systems developed for space and ground-based applications. In addition, it will give an outlook on future applications of such systems for X-ray and electron detection.

(15:00) N3C3-4, Development of CMOS strip sensors for tracking at the high luminosity LHC

C. Buttar

School of Physics and Astronomy, University of Glasgow, Glasgow, UK

On behalf of the Strip CMOS collaboration
CMOS based sensors based on movement of charge by diffusion are too slow and not sufficiently radiation hard for use in the high rate and hostile radiation environment of the Large Hadron Collider. Sensors have now been developed using commercial CMOS processes that allow relatively high bias voltages to be applied or use high resistivity substrates, allowing collection of charge by drifting in an electric field. The drift signal should be sufficiently fast to operate in a high rate environment and be less sensitive to radiation effects. CMOS sensors are being developed with a view to replacing the baseline silicon strip sensors based on planar silicon technology that are proposed for the HL-LHC Tracker Upgrades. This paper describes the characterization of CMOS sensors manufactured using a high-voltage CMOS process and a high-resistivity CMOS process. The charge collection and noise of the two sensors types before and after irradiation measured with sources and in testbeams will be presented and results from the two technologies compared.

(15:20) N3C3-5, Development of New 3D Pixel Sensors for Phase 2 Upgrades at HL-LHC

G.-F. Dalla Betta1,2, M. Boscardin3,2, R. Mendicino1,2, S. Ronchin3, D. Sultan1,2, N. Zorzi3,2

1Department of Industrial Engineering, University of Trento, Trento, Italy
2TIFPA, INFN, Trento, Italy
3CMM, Fondazione Bruno Kessler, Trento, Italy
We report on the development of new 3D pixel sensors for the Phase 2 Upgrades at the High-Luminosity LHC (HL-LHC). To cope with the requirements of increased pixel granularity (e.g., 50×50 or 25×100 µm2 pixel size) and extreme radiation hardness (up to a fluence of 2×1016 neq cm-2), thinner 3D sensors (~100 µm) with electrodes having narrower size (~ 5 µm) and reduced spacing (~ 30 µm) are considered. The paper will cover technological and design aspects, TCAD simulations, and initial results from the characterization of the first batch of these 3D sensors currently being fabricated at FBK on 6” wafers.

(15:40) N3C3-6, Development of Fine Pixel Detector for HEP Experiments Based on Innovative Double SOI Technology

S. Honda1, W. Aoyagi1, M. Asano1, K. Hara1, D. Sekigawa1, B. Subedi1, N. Tobita1, Y. Arai2, K. Kurachi2, T. Miyoshi2

1Pure and Applied Sciences, University of Tsukuba, Tsukuba, Japan
2INPS, High Energy Accelerator Research Organization (KEK), Tsukuba, Japan
Silicon-on-Insulator (SOI) technology is attractive for realizing fully-depleted monolithic pixel devices with fine pixel sizes. Such a device is ideal for high-energy physics experiments where fast signal collection is required with allowing fine pixel segmentation. Besides many advantages of SOI devices such as low leak current, fast response, immunity to SEE etc., the sensitivity to total ionization dose effects is an issue. The tolerance to TID effects has been substantially enhanced by employing double SOI structure where the potential of the second silicon layer (SOI2) is adjusted to compensate for the effects of holes accumulated in the insulator. The same structure is effective for suppressing the back-gate effect and crosstalk between the pixel nodes and the close-by electronics circuits. The effectiveness of the suppression is examined using dedicated TEGs (test element group) where the coupling capacitances and pick-up signals are probed directly with changing the potential to the SOI2. The SOI2 effectiveness in crosstalk suppression is evaluated quantitatively. FPIX2 is a double SOI pixel chip with a pixel size of 8 µm square, operated under a rolling shutter mode. The analog signals in the same column are extracted one by one, and are digitized by eight ADCs operated in parallel. The characteristics of FPIX2 irradiated with Cobalt gammas and 70-MeV protons are evaluated to detail, including signal collection, time response, inter-pixel cross talk, and any changes in operation conditions. Successful operation of monolithic detectors with such fine-pixel size and fast response encourages us to adopt the sensor to future precision high energy trackers such as at the ILC.