Program Listings

N4C4 Timing and Analysis Techniques

Thursday, Nov. 5 14:00-16:00 Pacific Salon 1&2

Session Chair: Giovanna Lehmann Miotto, CERN, Switzerland; Stefan Ritt, Paul Scherrer Institute, Switzerland

(14:00) N4C4-1, The TOTEM Precision Clock Distribution System.

F. S. Cafagna

INFN, Bari section, Bari, Italy

On behalf of the TOTEM Collaboration

To further extend the measurement potentialities for the experiment at luminosities where the pile-up and multiple tracks in the proton detectors make it difficult to identify and disentangle real diffractive events from other event topologies, TOTEM has proposed to add a timing measurement capability to measure the time-of-flight difference between the two outgoing protons. For such a precise timing measurements, a clock distribution system that empowers time information at spatially separate points with picosecond range precision, is needed. For the clock distribution task, TOTEM will adopt an adaptation of the Universal Picosecond Timing System, developed for the FAIR (Facility for Antiproton and Ion Research) facility at GSI, actually installed as BUTIS system. In this system an optical network, using dense wavelength division multiplex (DWDM) technique, is used to transmit two reference clock signals from the counting room to a grid of receivers in the tunnel. To these clocks another signal is added that is reflected back and used to continuously measure the delays of every optical transmission line; these delay measurements will be used to correct the time information generated at the detector location. The usage of the DWDM make it possible to transmit multiple signals generated with different wavelengths, over a common single mode fibers. Moreover allows to employ standard telecommunication modules conform to international standards like the ITU (International Telecommunications Union) ones. The prototype of this system, showed that the influence of the transmition system on the jitter is negligible and that the total jitter of the clock transmission, is practically due to the inherent jitter of clock sources and the end user electronics. Details on the system design, installation in the TOTEM detector and tests will be given in this contribution.

(14:20) N4C4-2, The CMS Timing and Control Distribution System

J. Hegeman¹, J.-M. Andre², U. Behrens³, J. Branson⁴, O. Chaze¹, S. Cittolin⁴, G.-L. Darlea⁵, C. Deldicque¹, Z. Demiragli⁵, M. Dobson¹, S. Erhan⁶, J. Fulcher¹, D. Gigi¹, F. Glege¹, G. Gomez-Ceballos⁵, M. Hansen¹, A. Holzner⁴, R. Jimenez-Estupinan¹, L. Masetti¹, F. Meijers¹, E. Meschi¹, R. Mommsen², S. Morovic¹, V. O'Dell², L. Orsini¹, C. Paus⁵, M. Pieri⁴, A. Racz¹, D. Simelevicius⁷, J. Troska¹, P. Vichoudis¹, P. Zejdl²

¹CERN, Geneva, Switzerland
²FNAL, Chicago, Illinois, USA
³DESY, Hamburg, Germany
⁴University of California, San Diego, San Diego, USA
⁵Massachusetts Institute of Technology, Cambridge, Massachusetts, USA
⁶University of California, Los Angeles,, Los Angeles, USA
⁷Vilnius University, Vilnius, Lithuania

The Compact Muon Solenoid (CMS) experiment operating at the CERN (European Laboratory for Nuclear Physics) Large Hadron Collider (LHC) is in the process of upgrading several of its detector systems. Adding more individual detector components brings the need to test and commission those components separately from existing ones so as not to compromise physics data-taking. The CMS Trigger, Timing and Control (TTC) system had reached its limits in terms of the number of separate elements (partitions) that could be supported. A new Timing and Control Distribution System (TCDS) has been designed, built and commissioned in order to overcome this limit. It also brings additional functionality to facilitate parallel commissioning of new detector elements. We describe the new TCDS system and its components and show results from the first operational experience with the TCDS system in CMS.

(14:40) N4C4-3, Fundamentals of a Scalable Network in SPADnet-Based PET Systems

M. Bijwaard¹, C. Veerappan¹, C. Bruschini², E. Charbon¹

¹TU Delft, Delft, Netherlands
²EPFL, Lausanne, Switzerland

In SPADnet we have advocated the use of standardized photonic modules for modular assembly of PET systems. In this paper, we tackle the scalability problem, starting from synchronization. Since the photonic modules in a ring must ensure tens of picoseconds in timing accuracy, it is essential that the synchronization of each module be accurate, irrespective of the number of modules in a ring, the ring’s size, and the number of rings in the system. We propose a hybrid solution, where a hard-wired clock synchronization network is combined with a network-based clock offset estimator. This combination enables scalability while maintaining high precision. A novel least squares synchronization algorithm is optimized and implemented in hardware equipped with a delay line FPGA TDC, allowing picosecond clock synchronization. The solution is verified in an 8 node system.

(15:00) N4C4-4, Comparison of Interpolation Techniques for TDCs Implementation in FPGA

N. Lusardi, A. Geraci

DEIB, Politecnico di Milano, Milan, Italy

TDC architectures are particularly suited to be implemented into FPGA devices especially addressed to multi-channel applications. But, the TDCs in FPGA suffer the penalty of high integral nonlinearity (INL). Aim of this contribution is to compare different interpolation techniques used in TDC implementation in FPGA, outlining a methodology to choose the solution most suited to the technological characteristics of the FPGA device.

(15:20) N4C4-5, The CMS Fast Beams Condition Monitor Backend Electronics Based on MicroTCA Technology

A. A. Zagozdzinska^1,2

¹PH-CMX-DS, CERN, Geneva, Switzerland
²Faculty of Electronics and Information Technology, WUT (Warsaw University of Technology), Warsaw, Poland

On behalf of the BRIL Group

The Fast Beams Condition Monitor (BCM1F), upgraded for LHC Run II, is used to measure the online luminosity and machine induced background for the CMS experiment. The detector consists of 24 single-crystal CVD diamond sensors that are read out with a custom fast front-end chip fabricated in 130 nm CMOS technology. Since the signals from the sensors are used for real time monitoring of the LHC conditions they are processed by dedicated back-end electronics to measure separately rates corresponding to LHC collision products, machine induced background and residual activation exploiting different arrival times. The system is built in MicroTCA technology and uses high speed analog-to-digital converters. The data processing module designed for the FPGA allows a distinguishing of collision and machine induced background, both synchronous to the LHC clock, from the residual activation products based on arrival time measurements. In operational modes of high rates, consecutive events, spaced in time by less than 12.5 ns, result in signal pileup. Hence, novel signal processing techniques are deployed to resolve overlapping peaks. The high accuracy qualification of the signals is crucial to determine the luminosity and the machine induced background rates for the CMS experiment and the LHC. The architecture of the back-end electronics and the signal processing techniques will be presented and its performance thus far using data taken in LHC Run II.

(15:40) N4C4-6, New Developments in MicroTCA Instrumentation Standards Extensions for Physics and Industry

R. S. Larsen

Advanced Instrumentation Research, SLAC National Accelerator Laboratory, Menlo Park California, USA

On behalf of the PICMG xTCA for Physics Standards International Collaboration

In 2009 a group of physics laboratories joined the 250-member industry open source standards group PICMG [1] to develop extensions to a new instrumentation standard known as ATCA[2]. The motivation was a highly reliable system that could support the latest high performance low cost serial gigabit technologies and field programmable gate array (FPGA) devices. The ATCA standard consisted of two related form factors, a large carrier card (blade) and a smaller daughter-card called the Advanced Mezzanine Card, AMC. The industrial group also created a smaller crate design for the small AMCs called MicroTCA that maintained all the key performance features of the ATCA system. Both cards were designed so support a Rear Transition Module (RTM) but only the ATCA version was implemented in industry. The physics group first designed an entirely new crate and MicroRTM (µRTM) with a standard interface in which a single AMC processor such as an ADC-DAC and FPGA with different µRTM adapters can serve multiple applications. A simple FPGA AMC could also process fast and slow analog and digital interlocks, motion control and piezo tuning drivers. All basic infrastructure crates, power units, cooling, modules, controllers and hub switchers quickly became available from multiple commercial suppliers. Standard extensions of both hardware and software have continued to evolve with a powerful new auxiliary Rear Transition Module backplane and Rear Power Module system, access to wider bandwidth Serial channels and processing power and Extended RTMs that distribute fast RF signals on the RTM backplane to eliminate large numbers of external cables. New software standard extensions to encourage broad lab-industry interoperability consisting of Standard Process, Device, Application Program Interface (API) and Hot Plug procedure packages are close to approval and release. Present and future standards extension roadmaps will be summarized.