N2C2  Circuits for SiPM and Timing

Tuesday, Nov. 3  14:00-16:00  San Diego

Session Chair:  Lorenzo Fabris, Oak Ridge National Laboratory, United States; Shaorui Li, Brookhaven National Laboratory, United States

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(14:00) N2C2-1, A 16-Channel Read-Out ASIC for PET Application

H. Xu, M. Perenzoni, N. Massari, A. Gola, A. Ferri, C. Piemonte, D. Stoppa

Integrated Radiation and Image Sensors, Fondazione Bruno Kessler, Trento, Italy

This paper presents an ASIC in 150nm CMOS technology, aiming at Silicon Photomultiplier (SiPM) readout for positron Emission Tomography (PET) application. The chip includes 16 channels, and each is composed of a current buffer, a validation block, a charge sensitive amplifier, a 10-bit ADC and a 12-bit TDC, occupying a size of 2.8×2.2 mm2. An 11.5nC input charge range was designed for a maximum input current of 20mA per channel. The gamma characterization was conducted with 3×3 mm2 SiPMs (RGB-FBK) coupled to 3×3×5mm3 LYSO scintillator, showing an energy resolution of 11.2% and Coincident Resolving Timing (CRT) of 663ps. To improve the timing performance, an updated ASIC has been already submitted for fabrication.

(14:20) N2C2-2, A New solution of Time Synchronization in All-Digital PET Based on TDC

L. Fang1, B. Zhang1, L. Yan1, J. Dai1, W. Wang2, Q. Xie3, J. Li3

1Wuhan Digital PET Technology Co., Ltd., Wuhan, Hubei, China
2The General Hospital of People's Liberation Army (301 hospital), Beijing, China
3Huazhong University of Science and Technology, Wuhan, Hubei, China

High-accuracy time synchronization is one of the most important issues for basic detector modules (BDMs) in the all-digital PET. The existing synchronization solutions are hard to extend as strict requirement to the wires and interfaces. Once the number of BDM changed, the whole system's synchronization should be rebuilt from the beginning. In this paper, a new high-accuracy time-sync solution based on TDC with a feather of flexible extensible has been designed and implemented. It provides a protocol for time correction by any of two detectors through a simple communication: Each TDC implemented in every detector will record the accurate time of both the ASK and REPLY messages and sends the time-records to the other. By the exchange of time-records, the two detectors will calculate the time differences and correct it to for time synchronization. This method promise a lower requirement to the interfaces, and much simpler connecting and easier to be extended. And it can always offer a high accuracy time synchronization by just a soft correction, despite of the change or development of the PET system such as increasing or decreasing detectors.

(14:40) N2C2-3, Towards Picoseconds Timing Accuracy, Low Power and Low Area Time-to-Digital Converter Made in CMOS 65 nm for Pixel Integration in Single Photon Counting Modules

N. Roy, F. Nolet, M.-O. Mercier, R. Fontaine, J.-F. Pratte

Institut Interdisciplinaire d'Innovation Technologique (3IT), Université de Sherbrooke, Sherbrooke, Qc, Canada

Time-of-flight measurements have become an important concern in high energy physics and medical imaging modalities such as positron emission tomography (PET). PET scanners could benefit from this technique by raising the image’s contrast and creating real time images, increasing time efficiency. To achieve such advantages, timing accuracy must be in the range of ps. For example, a lot of work is done with scintillators for raising the quantity of prompt photons generated by Cherenkov radiations, hot intraband luminescence and quantum dots spontaneous emission. The detectors and the electronics coupled to those scintillators also need to offer a timing accuracy in the ps range. Many single photon counting modules (SPCM) use shared time-to-digital converters (TDC) for several pixels. It provides timestamps to only few detected photons at a time as well as creating a pixel-to-pixel skew, thus restricting the timing accuracy of the whole system. A more suitable approach for prompt photon detection is to provide a TDC per pixel in conjunction to a single photon avalanche diode (SPAD) based detector integrated in 3D. To achieve this, it requires a very low area TDC with minimum power consumption. Moreover, both the jitter and the resolution must be in the range of ps to benefit from prompt photon timing accuracy. This paper proposes a 25 × 50 µm2 single stage vernier TDC made in TSMC CMOS 65 nm. Measurements have shown an integral non-linearity (INL) of 3 LSB and a differential non-linearity (DNL) of 0.34 LSB maximum at a resolution of 15.2 ps. A power consumption of 160 µWrms at 100 Kevents/sec has also been measured. These measurements are very promising and it is a very good starting point to reach ps timing accuracy.

(15:00) N2C2-4, Readout Circuit and Data Acquisition System for a SPAD Array Designed in TSMC CMOS 65 Nm

M.-O. Mercier

Electrical and Computer engineering, Institut Interdisciplinaire d'Innovation Technologique (3IT), Université de Sherbrooke, Sherbrooke, Québec, Canada

Single photon avalanche diodes (SPAD) are solid-state photodetectors with promissing performance regarding timing resolution as well as single photon measurement and are used in two types of Silicon photomultiplier (SiPM) technology: analog SiPM (aSiPM) and digital SiPM (dSiPM). An aSiPM produces current according to the number of detected photons whereas the dSiPM generates a number of fired SPAD. SPAD arrays can be operated in time correlated single photon counting (TCSPC) or in time uncorrelated single photon counting (TUSPC). In TCSPC mode, a TDC is required and a tradeoff between power consumption, area and single photon time resolution must be made. One way to answer to all requirements is to include a TDC per pixel in a 3D stack of ASICs. 3D integration of a SPAD array over a SPAD readout circuit array allows to get both the max fill factor and a high photon detection efficiency for the SPAD array. In this paper, we propose an architecture for the readout of an array of SPAD circuit and a data aquisition system (DAQ) being able to work in both TCSPC and TUSPC mode of operation. Thanks to the electronic flexibility of the 3D integration, each pixel can contain a TDC that provides time stamps for individual detected events or counts the number of event depending on the mode of operation. The pixels are polled by a token per column and the data are sent with the pixel address and the global system time to the DAQ FPGA. These data are then conditioned and sent to the GUI for analysis. Preliminary results of the integrated circuit (IC) with the DAQ have shown a IC-FPGA data rate of 6 M events/s in TCSPC mode and 12.5 M events/s in TUSPC mode. The FPGA-GUI data rate is of 20 k events/s in TCSPC mode and 41 k events/s in TUSPC mode.

(15:20) N2C2-5, Development and Evaluation of a Practical Multiplexing Readout of a Large SiPM Array for a Flat-Panel DOI PET Detector Applications

Z. Wang1,2, X. Sun3, K. Lou3, J. Meier3, R. Zhou2, C. Yang2, X. Zhu1, Y. Shao3

1Radiation Physics, The University of Texas MD Anderson Cancer Center, Houston, Texas, United States
2Physical Science and Technology, Sichuan University, Chengdu, Sichuan, China
3imaging physics, The University of Texas MD Anderson Cancer Center, Houston, Texas, United States

One challenge in developing a large size flat-panel PET detector with depth-of-interaction (DOI) measurement (based on dual-ended-scintillator readout) is to substantially reduce the number of readout channels while still maintain good detector performance. Previously investigated multiplexing readout methods are not well suited due to high dark counts accumulated from 400 SiPMs on each detector end and severe position-dependent waveform distortion or shift of event arrival timing among different channels. The aim of this study was to design and implement a practical multiplexing circuit to solve this problem. We simulated both capacitor and resistor based circuits to read out latest SiPM arrays with a common cathode which has not been fully studied yet, critically analyzed the charge sharing among different channels and the impact to the overall detector performance, and explored different circuit designs and optimizations for reading a 20x20 SiPM array. Experimental studies based on simulation guidance were also conducted. Results show that using a resistor network to divide the charge of signals from a SiPM into two independent branches, with the division of charge based on the SiPM position in the network can achieve desired overall performance requirement. To eliminate the timing shift existing in most resistor multiplexing circuits, every path of charge sharing with the same overall resistance was implemented. The ratio of resistor values were determined by both providing the best timing resolution and impedance matching with the further processing electronics. Excellent flood-source crystal map of 1024 LYSO crystals (each with 2x2x30 mm size) was achieved with 1.8 to 4.7 peak-valley ratios, and 17% energy resolution. In conclusion, we have designed and implemented a unique and practical resistor-based multiplexing circuit that can be readily applied for reading out a large SiPM array with good detector performance.

(15:40) N2C2-6, A CMOS Self-Triggered Gated Integrator Circuit for SiPM Readout in SPECT Applications

P. Trigilio1,2, M. Gerosa1, P. Busca1,2, B. Nasri1,2, C. Fiorini1,2

1Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milano, Italia
2Sezione di Milano, Istituto Nazione di Fisica Nucleare, Milano, Italia

Energy resolution in multi-tracer SPECT detectors plays a major role, as spectral lines emitted by different radionuclides have to be distinguished. In the electronic circuit for the readout of SiPMs used in a SPECT system, the choice of the processing filter is therefore essential to provide the best possible energy resolution. We identified the gated integrator filter as an excellent candidate for this kind of application, mainly because of its capability to reduce ballistic deficit in the signal processing, allowing for a quasi-complete light collection with a filtering time considerably shorter with respect to the ones needed by time-invariant circuits. We developed a single-channel prototype circuit in CMOS 0.35 µm technology to validate our preliminary studies and measurements. The circuit features a current buffer input stage with the possibility to tune the input voltage in a 1 V range with 6 bit resolution and a filtering section to integrate the signal rejecting the baseline component originated by the dark count current of the SiPM. A discriminator block recognises the arrival of the signal and starts the integration phase; a control section generates the gating interval, selectable in a range between 200 ns and 11 µs in order to make the circuit suitable for various scintillator type, and controls all the timing phases of the circuit. A comparison between the energy resolution achievable using a time invariant RC filter and the one obtainable with the presented IC is done, showing an expected improvement in energy resolution at the 140 keV 99mTc peak. Experimental results of the prototype when coupled to a SiPM will be reported.