N2D3  LHC Trigger Upgrades

Tuesday, Nov. 3  16:30-18:10  Golden West

Session Chair:  Martin Purschke, Brookhaven National Lab, United States; Andreas Kugel, ZITI, Heidelberg University, Germany

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(16:30) N2D3-1, The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

T. Lazovich

Department of Physics, Harvard University, Cambridge, MA, USA

On behalf of the ATLAS Muon Collaboration
The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can both meet the low latency requirements of the trigger system and cope with the high background rates of the high luminosity LHC.

(16:50) N2D3-2, A Pattern Recognition Mezzanine Based on Associative Memory and FPGA Technology for Level- 1 Track Triggers for the HL-LHC Upgrade

F. Palla1, G. Fedi1, G. Magazzu'1, D. Magalotti2,3, L. Servoli2, G. M. Bilei2

1INFN - Pisa, Pisa, Italy
2INFN - Perugia, Perugia, Italy
3Universita` di Modena e Reggio Emilia, Modena, Italy
The increase of luminosity at HL-LHC will require the introduction of tracker information at Level-1 trigger system for the experiments to maintain an acceptable trigger rate to select interesting events despite the one order of magnitude increase in the minimum bias interactions. To extract in the required latency the track information a dedicated hardware has to be used. We present the tests of a prototype system (Pattern Recognition Mezzanine) as core of pattern recognition and track fitting for HL-LHC ATLAS and CMS experiments, combining the power of both Associative Memory custom ASIC and modern Field Programmable Gate Array (FPGA) devices.

(17:10) N2D3-3, The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

G. Drake

High Energy Physics, Argonne National Laboratory, Lemont, Illinois, USA

On behalf of the ATLAS Tile Calorimeter Group
We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features, including power system redundancy, data processing redundancy, 10 Gbps optical links, and a Kintex-7 FPGA with single-event upset mitigation. To date, we have built a Demonstrator – a fullyfunctional prototype of the new system. Performance results, radiation tolerance measurements, and plans going forward will be presented.

(17:30) N2D3-4, gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

S. Tang, M. Begel, H. Chen, F. Lanni, H. Takai, W. Wu

Brookhaven National Laboratory, Upton, USA
The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger for Phase-I upgrade of the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx UltraScale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. A pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance of pre-prototype and trigger algorithm will be presented. We will also present the design of the gFEX board with UltraScale and discuss how it is being implemented. Although the board is being designed specifically for the ATLAS experiment, it is sufficiently generic that it could be used for fast data processing at other HEP or NP experiments.

(17:50) N2D3-5, Operation and Performance of the Upgraded CMS Calorimeter Trigger in LHC Run 2

P. R. Klabbers

University of Wisconsin, Madison, WI, USA

On behalf of the CMS Collaboration
The Large Hadron Collider (LHC) at CERN is preparing for the physics program for Run 2. The center-of-mass energy has risen from 8 to 13 TeV and the instantaneous luminosity will increase for both proton and heavy-ion running. This will make it more challenging to trigger on interesting events since the number of interactions per crossing (pile-up) and the overall trigger rate will be significantly larger than LHC Run 1. The Compact Muon Solenoid (CMS) experiment has installed a two-stage upgrade to their Calorimeter Trigger to ensure that the trigger rates can be controlled and the thresholds can stay low, so that physics data collection will not be compromised. The first-stage upgrade is installed and includes new electronics and duplicated optical links so that the LHC Run 1 CMS calorimeter trigger is still functional and algorithms can be developed while data taking continues. The second-stage will fully replace the calorimeter trigger at CMS with AMC form-factor boards and an optical link system, and require that the updates to the calorimeter back-ends, the source of the trigger primitives, are also installed and operational. The stage-2 system’s boards will utilize Xilinx Virtex 7 FPGAs and have hundreds of high-speed links operating at up to 10 Gbps to maximize data throughput. The integration, commissioning, operation, and performance of stage-1 for 2015 data taking and stage-2 for triggering in 2016 will be described.