N5A2  Waveform Sampling, ADC, and Data Transmission

Friday, Nov. 6  08:30-10:10  San Diego

Session Chair:  Yun Chiu, University of Texas at Dallas, United States; Shaorui Li, Brookhaven National Laboratory, United States

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(08:30) N5A2-1, The TARGETX ASIC for the Belle II Muon Detector Scintillator Upgrade

G. Varner, B. Edralin, I. Mostafenezhad, X. Shi

Physics and Astronomy, Univ. of Hawaii, Honolulu, HI, USA
In order to cope with the much higher backgrounds expected for the Belle II and SuperKEKB upgrades, the KLong and Muon (KLM) innermost barrel layers and endcap resistive plate chambers have been replaced with wavelength-shifting fiber embedded scintillator strips. Hamamatsu silicon photomultipliers (MPPCs) are used to instrument these strips.While the individual photo-electron resolution is expected to deteriorate due the neutron dose, the use of waveform sampling ASICs for readout will allow gain and threshold tracking, to compensate for these effects. Instrumentation of the more than 20,000 channels of readout is achieved in a very cost-effective manner using a variant of an ASIC initially designed for low-cost instrumentation of a future Cherenkov Telescope Array. The TARGETX is a 16-channel, 1 GSa/s Switched Capacitor Array transient waveform recorder with built-in, encoded triggering and 16k storage samples per channel storage depth. Measured performance meets or exceeds all requirements. Over 25,000 channels have been fabricated and results from the production verification will be reported.

(08:50) N5A2-2, CASCA: a Readout ASIC for a TPC Based X-Ray Polarimeter

H. Zhang1,2, Z. Deng1,2, L. He1,2, H. Li2, H. Feng2, Y. Liu1,2

1Key Laboratory of Particle & Radiation Imaging (Tsinghua University), Ministry of Education, Beijing, China
2Department of Engineering Physics, Tsinghua University, Beijing, China
The paper present the second version prototype ASIC (CASCA: Charge Amplifier with Switched Capacitor Array) for a TPC based X-ray polarimeter. It measures two dimensional photoelectron tracks generated by the incident X-ray photons with one dimensional strip readout. The other dimension is calculated by the drift time from the signal waveform. In order to achieve 100 µm track resolution fine pitch strips were used, requiring high density readout electronics with 20 MSPS waveform sampling capability. CASCA integrated 32 channel full function signal processing circuits and was fabricated in 0.18µm CMOS process. Each channel consisted of a charge sensitive preamplifier, a CR-RC shaper with a peaking time of 25 ns, a baseline holder, a discriminator and a 64-cell switched capacitor array (SCA). The analog front-end and the SCA circuits were implemented and verified in two separate chips in the previous prototypes. Several modifications were also made, such as using native NMOS capacitor to store the samples for its high density and large dynamic range and adding a reset switch for each sample cell to reduce the fixed pattern noise. The test results of the first prototypes show that the equivalent noise charge (ENC) was less than 920e with ~5pF input capacitance. The INL (Integrated Nonlinearity Error) was better than 0.81% and the center-of-gravity time jitter was measured to be no more than 3.5 ns. The noise of the SCA alone was tested to be 1.4 mV with 312.5 kHz sine wave, 50 MSPS sampling rate and 5 MHz readout rate. The effective resolution was 9.5 bit considering 1V dynamic range. The new ASIC has been received and the tests of the new ASIC are undergoing. The detailed design and test results will be present in this paper.

(09:10) N5A2-3, The IRSX ASIC for the Belle II Imaging Time of Propagation Detector

G. Varner1, M. Andrew1, L. Macchiarulo1, K. Nishimura2, L. Wood3

1Physics and Astronomy, Univ. of Hawaii, Honolulu, HI, USA
2SLAC National Accelerator Laboratory, Palo Alto, CA, USA
3Pacific Northwest National Laboratory, Richland, WA, USA
The highly successful Belle detector is being upgraded for its new mission to search for physics beyond the standard model in the intensity frontier of flavor physics. To maximally exploit the physics opportunities provided by 50 times larger data sets, significant improvements to the particle identification detector subsystems are being made. In the barrel, a novel detector, the imaging Time Of Propagation (iTOP) detector is under construction. This iTOP detector uses 2x16 arrays of 16- channel, 30-40ps single photon timing resolution Micro-Channel Plate Photomultiplier Tubes (MCP-PMTs) to precisely record the relatively small number of Cherenkov photons generated in a 20mm thick, highly polished quartz radiator. Due to the very limited radial and axial space available, and forseen need to access and replace PMTs and fiber transceivers, the readout electronics must fit into a very compact space. To meet these demanding requirements the IRSX ASIC has been developed. This 8-channel Switched Capacitor Array device records single photon transient waveforms at Giga-sample per second rates and uses built-in thresholding for region-of-interest Belle II trigger matching. At 4 GSa/s, the 32k storage cells per channel provides 8 microseconds of buffering, sufficient to accommodate the planned 5.2 microsecond trigger latency. In total 8,192 channels of readout have been fabricated, with iTOP detector module installation starting in autumn 2015. Design and production test performance of these ASICs will be reported.

(09:30) N5A2-4, A 32-Channel 13-Bit ADC for Space Applications

F. Bouyjou, O. Gevin, O. Limousin, E. Delagnes

IRFU, CEA, Gif sur Yvette Cedex, France
This paper presents a 13-bit, 2.56 µs conversion time, 2 V input range, 32-channel single slope analog-to-digital converter (ADC) called OWB-1 implemented in a 0.35 µm CMOS technology. An interpolator composed by a Delay Lock Loop (DLL) is used to increase the time resolution of the conversion counter by a factor of 32, while keeping a low power consumption and ensuring the high dynamic performance of the ADC. Measurements performed on the ADC have shown that the noise is better than 0.86 LSB over the full conversion range, its differential nonlinearity (DNL) is in the range of -0.28/+0.31 LSB and its integral nonlinearity (INL) is within -1.3/+2.1 LSB, for a power consumption of 57 mW. A new temperature compensation system based on a servo loop has also been integrated in the chip to compensate for temperature effects in the -40 °C to +40 °C range. Special design techniques have been used to increase the tolerance of the ASIC to Single Event Latchup (SEL). OWB-1 is currently foreseen for two space missions: SVOM (Franco chinese’s mission) and LOFT (ESA mission).

(09:50) N5A2-5, Radiation-Tolerant IP-Cores for 2Gbps Serial Links for the Data Readout in Future LHC Experiments

G. Magazzu1, F. Brewer2, M. Miller2, D. Wang2

1Sezione di Pisa, INFN, Pisa, Italy
2ECE Department, University of California, Santa Barbara, Santa Barbara, CA, USA
The increase of luminosity foreseen for the future upgrades of the Large Hadron Collider at CERN will require the complete re-design of the Front-End electronics in all the experiments. One of the goals of the RD53 collaboration is the development of a full set of radiation-tolerant IP-cores in view of the design in 2016 of the first prototype of the new Front-End circuit for the pixel detectors of the ATLAS and CMS experiments. In this framework we designed radiation-tolerant 2Gbps Serializer and Deserializer modules and 3GHz SLVS differential transmitter and receiver pads in a commercial 65nm CMOS technology. IP-cores will be described in detail as well as results of test and characterization of first prototypes, including results of irradiation tests with X-Rays (Total Ionizing Dose effects) and heavy ions (Single Event Effects).