Tutorial Title: Design for Testability (DFT) for Deep Submicron Integrated Circuits

Speaker: Dr. Waleed K. Al-Assadi, Department of Electrical and Computer Engineering Missouri University of Science and Technology (formerly, University of Missouri-Rolla)

Abstract: Scaling down of the CMOS technology has brought a tremendous benefits as well as serious challenges. As complex system-on-chip (SoC) ICs with hundreds of million of transistors on die are becoming reality, the challenges of testing such circuits during the manufacturing phase are becoming difficult. Low test coverage has contributed to unacceptable low yields, and imposes a serious problem for the reliability of the product. ICs fabricated in nanometer CMOS technology have suffered excessive leakage currents that lead to large power dissipation, on-chip noise due to capacitive, inductive and resistive coupling that cause violations to the timing parameters of the design, and moreover, a large potion of physical failures cannot be represented by the classical stuck-at fault modeling. This tutorial will provide the state of the art in testing complex SoCs in the semiconductor industry. We will cover the issues of the economic of the test, test techniques like scan, built-in self test (BIST), embedded memory test, at-speed and delay test, and current testing (IDDQ) test, and future trends in testing designs in nanoscale technology. The presenter faced the problems of producing highly testable and reliable ICs with reasonable high yield while being with IBM Microelectronics. He developed and implemented design for test methodologies for the IBM PowerPC embedded processors.

Prospective Audience: This tutorial is intended for students who want to pursue career in semiconductor industry, professional who in the area VLSI systems design, and researchers who want to develop CAD tools and algorithms in VLSI testing.

Presenter’s Biography: Dr. Waleed Al-Assadi is currently an Assistant Professor with the Department of Electrical and Computer Engineering, Missouri University of Science and Technology. He worked for AMD and IBM in the design, design for testability, and verification of microprocessors. His research interests are in VLSI systems design, testing, verification, CAD tools, and embedded systems. He holds four US patents.