Plenary Speakers

 

Dr. Anthony Yen

Title: Enabling manufacturing of sub-10nm generations of integrated circuits with EUV lithography

Abstract: EUV lithography enters high-volume manufacturing in 2019 to provide the necessary technology for continued scaling of integrated circuits. EUV exposure systems with a throughput of >140 wph at a dose of 20 mJ/cm² have become available in the field, using a source power of 250W. Concurrently, rate of power degradation has been driven down so that high system throughput can be maintained. ASML continues to improve the performance of EUV systems with higher throughput and tighter overlay specifications to further enhance their productivity and capability. At the same time, our phase-inclusive source-mask optimization maximizes the process latitude. For manufacturing with EUV lithography beyond the first generation, issues such as the stochastic behavior of photoresists and the three-dimensional nature of the photomask are being addressed to enable single patterning at lower values. Overcoming these limitations will allow EUV lithography to extend into the next decade with minimal use of double patterning. Finally, ASML has also started to develop the next-generation EUV exposure tool to enable continued scaling in semiconductor manufacturing.

Biography: Anthony (Tony) Yen is Head of ASML’s Technology Development Centers. From 2006 to 2017, he was with TSMC where he led the development of EUV lithography for high-volume manufacturing. From 1991 to 1997, as a researcher with Texas Instruments, he worked on techniques to enhance the practical resolution of microlithography. From 1997 to 2003, he was with TSMC where he first led development of lithography processes for TSMC's 0.25, 0.18, 0.15, and 0.13 micron generations of logic integrated circuits and then co-led infrastructure development for next-generation lithography technologies at SEMATECH. From 2003 to 2006 he was with Cymer where he headed its marketing organization. Tony received his BSEE degree from Purdue University and his SM, EE, PhD , and MBA degrees from MIT. He is a fellow of IEEE and SPIE, and a 2018 recipient of the outstanding alumnus (OECE) award from Purdue University School of Electrical and Computer Engineering. He holds over 100 patents on EUV lithography and related areas.