Invited Speakers

 

Jacopo Franco
Principal Member of Technical Staff

Title: Low Thermal Budget Dual-Dipole Gate Stacks Engineered for Sufficient BTI Reliability in Novel Integration Schemes

Abstract: Low thermal budget gate stacks will be required for novel integration schemes, such as 3D sequential stacking of CMOS tiers. We study the impact of a reduced thermal budget on BTI reliability, and we demonstrate interface dipole engineering to suppress the carrier-defect interaction and achieve sufficient nMOS PBTI and pMOS NBTI reliability without the customary post-deposition anneals.

Biography: Jacopo Franco is a Principal Member of Technical Staff at imec, Belgium. He received the B.Sc. (2005) and M.Sc. (2008) in Electronic Engineering cum laude from the University of Calabria - Italy, and the Ph.D. degree in Engineering summa cum laude from KU Leuven - Belgium (2013). His research focuses on the reliability of high-mobility channel MOSFETs, on modelling of oxide traps in novel MOS gate stacks or novel integration schemes, and on time-dependent variability in nanoscale devices. He has (co-)authored 200+ publications in international journals and conference proceedings, including 20+ invited papers, 1 book, 3 book chapters, 2 international patent families. He received the Best Student Paper Award at IEEE SISC (2009), and the EDS Ph.D. Student Fellowship (2012). He is one of the recipients of the EDS Paul Rappaport Award (2011), and the Best (2012), Outstanding (2014), and Best Student (2016) Paper Awards at IRPS. He is serving as a Technical Program Committee member at IRPS, IIRW, ESREF, WoDiM conferences, and as an Editor of IEEE Transactions on Device and Materials Reliability.