Tutorial A

 

NAOTO HORIGUCHI, imec, Belgium

Title: Logic CMOS device scaling scenarios toward N2

Abstract: In recent CMOS scaling, gate and metal pitch scaling is slowing down and not enough to enable expected area reduction. Instead, track height (number of metal lines/standard cell) scaling is a main driver for CMOS area scaling today and in the future. For further 2-dimensional device area scaling or functional area scaling, device stacking technologies, such as complementary FET (CFET) and 3D sequential integration are attractive options. This tutorial starts with enablers for further scaling of contacted poly pitch (CPP) and fin pitch (FP). In addition to patterning cliff, contact resistance and gate-last integration limits further CPP and FP scaling, respectively. Key technologies for CPP/FP scaling are contact resistance reduction, spacer k value reduction, gate-last integration scaling, fin width scaling and gate-all-around (GAA) architecture introduction.

In the second part of this tutorial, the discussion centers on how to enable aggressive track height scaling toward single fin standard cell architectures, which is common in N2 node. There are two concerns in aggressive track height scaling; drive current degradation per device from fin number reduction forced by track height scaling and wiring congestions from small device area. Mobility enhancement by strain boosters and high mobility channel is important to compensate drive current degradation per device. GAA, especially stacked nanosheet is an attractive device architecture not only to improve electrostatics at short gate length but also to improve drive current in single fin architectures. Wiring congestions from small track height have to be improved by so called “scaling boosters” such as self-aligned gate contact and metal gate cut. Finally, paths for device stacking and their integration challenges are discussed. CFET, which is consisted of stacked NMOS and PMOS, is an interesting option for further area scaling of logic and SRAM. 3D sequential integration enables functional area scaling by different functions, such as logic, memory, analog and I/O.

Biography: Naoto Horiguchi is the director of the CMOS device scaling program at imec, Leuven, Belgium currently. He started his career in the semiconductor device R&D industry in Fujitsu Laboratories Ltd. in 1992. In 1992-1999, he was engaged in device development by using semiconductor nano structures in Fujitsu laboratories Ltd. and University of California, Santa Barbara. In 2000 to 2006, he was engaged in 90-45nm CMOS technology development in Fujitsu Ltd. as a lead integration engineer. From 2006, he is with Interuniversity Microelectronics Center (IMEC), Leuven, Belgium, where he is engaged in advanced CMOS device R&D together with worldwide universities and industrial partners. His current focus is CMOS device scaling down to 2nm technology node and beyond. He holds more than 20 international patents and authored or co-authored more than 250 technical papers and international conferences.