Short Course 1

Machine Learning Driven Chip Design Delivers Performance and Productivity Revolution

Kumkum Bhatt
Cadence

Abstract: Engineering teams are under increasing pressure to deliver chips as fast as possible, often spending significant time tuning the implementation flow for each project. During this presentation, Cadence will show how Cerebrus machine learning RTL to GDS chip design flow optimization, automates this whole process, delivering better PPA more quickly.