Invited Speaker

Advanced Compact Modeling for Transistor Aging: Trap-based Approaches and Mixed-mode Coupling

Runsheng Wang (Peking University)

Biography: Runsheng Wang received the B.S. and Ph.D. (highest honors) degrees from Peking University, Beijing, China, in 2005 and 2010, respectively. From November 2008 to August 2009, he was a Visiting Scholar with Purdue University, West Lafayette, IN, USA. He joined Peking University in 2010, where he is currently a Full Professor at the School of Integrated Circuits. He also serves as the Associate Dean of the School of EECS. He has authored/coauthored 1 book, 4 book chapters, and over 190 scientific papers, including more than 40 papers published in International Electron Devices Meeting (IEDM) and Symposium on VLSI Technology (VLSI-T). He has been granted over 20 US patents and over 30 Chinese patents. His current research interests include nanoscale CMOS devices, characterization and reliability, design-technology co-optimization (DTCO) and EDA, emerging technologies and circuits for new-paradigm computing. Dr. Wang was awarded the IEEE EDS Early Career Award by the IEEE Electron Device Society (EDS), National Distinguished Young Scholars by National Natural Science Foundation of China (NSFC), Natural Science Award (First Prize) by the Ministry of Education (MOE) of China, and many other awards. He serves on the Editorial Board of IEEE TRANSACTIONS ON ELECTRON DEVICES and SCIENCE CHINA: Information Sciences. He has also served on the Technical Program Committee of many IEEE conferences, including IEDM, IRPS, EDTM, IPFA, etc.