Abstract

As semiconductor technology advances into nanometer territory, the antenna problem has caused significant impact on routing tools. The antenna effect is a phenomenon of plasma-induced gate oxide degradation caused by charge accumulation on conductors. It directly influences reliability, manufacturability and yield of VLSI circuits, especially in deep submicron technology using high density plasma. Furthermore, the continuous increase of the problem size of IC routing is also a great challenge to existing routing algorithms. This talk presents a novel framework for multilevel full-chip routing with antenna avoidance using built-in jumper insertion approach. Compared with the state-of-the-art multilevel routing, the experimental results show that the novel approach reduces 100% antenna-violated gates and results in smaller wire length, fewer vias, and smaller delay.

Admission is free! Make your reservation by February 2, call Ken Hsu at 585-475-2655.

Biography

Sao-Jie Chen received B.S. and M.S. degrees in electrical engineering from the National Taiwan University, Taipei, Taiwan. Also, he received a Ph.D. in electrical engineering from the Southern Methodist University, Dallas, USA. He is currently is a Professor of Electrical Engineering at the National Taiwan University. He was a visiting professor and researcher at UC San Diego, IBM TJ Watson Research Center, Yorktown Heights, and UW Madison. His current research interests include VLSI physical design automation, wireless LAN and Bluetooth IC design, and SOC hardware/software co-design and system-level design. Dr. Chen is a senior member of IEEE Circuits and Systems, and the IEEE Computer Societies, and the ACM.

This announcement is available for download in PDF format: Multilevel Routing with Jumper Insertion for Antenna Avoidance