Dec
17, 2010, Morning Session (parallel with Tutorial - II)
IP based Internet-of-Things for Smart Grids - a use case for Green ICT
By
Prateep Misra, Soma Bandyopadhyay, Jaydip Sen
Innovation Lab, Kolkata
Tata Consultancy Services
Ph:- +913366367295, Fax:- +913366367502
https://www.tcs.com
This tutorial will talk about how IP based networks can be used in Advanced Metering Infrastructure (AMI) of Smart Grids and the possible applications that can be deployed as "Internet-of-Things" on top of the IP network. We will discuss about the technology challenges in such implementations. Then we shall discuss in detail about two specific technology challenges - a) Semantic Interoperability and b) Security and Privacy.
Broad topics to be covered:
Prateep Misra - has over 18 years experience in software development, quality assurance, R&D and Project Management. He has worked in diverse areas such as Data Centers and IT Infrastructure, Process Control and Automation systems, Digital Signal Processing, Real-Time & Embedded System design and RFID & Sensors. Prateep has been instrumental in setting up the Center of Excellence of Digital Signal Processing and the RFID Technology Center in TCS. Prateep is an IEEE member and a Certified Software Quality Analyst. Prateep is a Research Area Manager in TCS Innovation Lab. He leads research programs in the area of Open Storage and Complex Event Processing. Prateep received his B. Tech in Instrumentation Engineering from Indian Institute of Technology, Kharagpur in 1990 and M. Tech in Control Systems Engineering from Indian Institute of Technology in 1993.
Soma Bandyopadhyay - Has more than 12.5 years of industry experience in the area of Embedded Systems, Digital Signal Processor and Wireless Communications.Since 2003, she has been associated with the Innovation lab of TATA Consultancy Services as a senior scientist. Presently her prime focus area is ubiquitous networking and computation, 4G-next generation broadband wireless MAC and Physical layer design. She has contributed towards the IEEE standard body on behalf of TCS. She is also involved in leading the development of 3GPP Long Term Evaluation (LTE/LTE-A) physical layer, IEEE-802.16d/e WMAN MAC stack development, protocol stack deve opment in RTOS. She worked on MPEG video decoder, dual core network processor target platform, Intel’s network processor, multiple device drivers, ATM & MPLS. Academically she is an M.Tech & B.Tech in Computer Science & Engineering from the University of Calcutta, India. She did her graduation in Physics (Hons.) from the same university.
Jaydip Sen - has been currently working with the Innovation Labs of
Tata Consultancy Services (TCS) in Kolkata. Prior to joining TCS, he had worked
with Oil and natural Gas Corporation Ltd, Dehardun, Oracle India Private Ltd.,
Dec
17, 2010, Morning Session (parallel with Tutorial - I)
Condition Monitoring of Oil-Paper Composite Insulation System of Transformers
By
Dr. Sivaji Chakravorti
IEEE PES Distinguished Lecturer & FNAE
Professor of
Electrical Engineering
Kolkata 700 032,
Email:
sivaji@ee.jdvu.ac.in
Large section of the power infrastructure in developed as well as developing countries is getting old. Significant numbers of equipment are nearing their designed end of life or have already exceeded it. Such equipment that is still in operation is very much prone to failures. In the context of the deregulated market economy, companies are forced to optimize asset utilization by operating existing infrastructure at ever-higher capacity levels, in many cases, exceeding nameplate ratings in order to defer capital investment in new facilities or in the refurbishment of existing facilities. Thus, most of the power utilities have focused their efforts on developing methods to assess the condition of capital intensive infrastructure in order to extend the life of existing infrastructure. Extending the life of such infrastructure will be possible only if companies can assess their current condition.
Reliable diagnostic tool for condition monitoring of capital intensive infrastructure such as transformers is also important from the point of view of reduction in maintenance cost. Currently power utilities are shifting from traditional Time Based Maintenance (TBM) to Condition Based Maintenance (CBM). This is due to the fact that in CBM, equipment will be maintained only if it is needed. On the other hand, in TBM often equipment is maintained when it is not required and often maintenance is not carried out when it is required.
The main aim of modern condition monitoring procedure is to carry out non-invasive measurement.There is still a lack of appropriate tools to diagnose aging effects of capital intensive infrastructure non-destructively and reliably in the field. New techniques have been published in the last decade and even before, which claim to offer reliable diagnostics. Some of these methods are based on changes of the properties of the components of the infrastructure. Such infrastructural properties are dependent on many factors, e.g. time, temperature, chemical composition, electrical properties etc. In engineering systems, most of these factors are to be considered during tests for many infrastructures.
This tutorial covers the following areas:
Failure Rate vs. Age of an Equipment,
Maintenance Strategies, How Preventive Maintenance Helps, Purpose of Diagnostic
Testing, Why Condition Monitoring, Causes of Insulation Degradation, Oil-Paper
Insulation System of Transformers.
Dissolved Gas Analysis, Furan Analysis,
Degree of Polymerization.
Moisture Distribution, Moisture Dynamics, Effects
of Moisture, Moisture Detection – Crackle Test, Karl Fischer Titration, Equilibrium
Curves, Comparison of Equilibrium Curves, ABB and Serena’s Equations, Moisture
Content in Paper, Moisture Management, Oil Reclamation.
Polarization Mechanisms in Dielectrics
Dielectric Response in Time-Domain.
·
Polarisation
and Depolarisation Current (PDC) Measurement, PDC Measurement – Test Set Up,
Typical PDC Measurement Results.
·
Recovery
Voltage Measurement (RVM), RVM Fundamentals, Polarization Spectrum, Typical RVM
Results.
Dielectric Response in Frequency-Domain
·
Frequency
Domain Spectroscopy (FDS), FDS equipment and analysis, Relating time and
frequency domain results.
Dr. Sivaji Chakravorti (born
1962) did his BEE, MEE and PhD from
For more information please visit https://www.schakravorti.info/
Dec
17, 2010, Afternoon Session (parallel with Tutorial - IV)
Energy-Efficient Robust Systems in Scaled CMOS and Beyond
Prof. Subhasish Mitra
Robust Systems Group
Department of Electrical Engineering
and the Department of Computer Science
Stanford University US
Complex electronic systems are an indispensable part of all our lives. The impacts of malfunctions in these systems continue to increase as systems become more complex, interconnected, and pervasive. Energy-efficiency of these systems is another major challenge. Robust system design is required to ensure that future systems perform correctly despite rising levels of complexity and increasing disturbances. Hardware failures are especially a growing concern because:
Existing validation and test methods barely cope with today’s complexity.Emerging multi-core and many-core system architectures, mainly driven by energy-efficiency objectives, make test and validation significantly difficult. New techniques will be essential to minimize the effects of defects and design flaws going forward.
For coming generations of silicon ICs, several failure mechanisms, largely benign in the past, are becoming visible at the system-level. Traditional guard-banding to ensure correct operation or traditional redundancy techniques for fault-tolerant computing are inadequate because they are highly energy-inefficient. A large class of future systems will require new energy-efficient techniques for tolerance of hardware errors during their operation.
Emerging nanotechnologies are inherently prone to high rates of imperfections. Nevertheless such technologies are being seriously explored to build highly energy-efficient systems of the future. The inherent imperfections must be overcome before such nanotechnologies can be harnessed with practical benefits to society.
This talk will address these outstanding challenges, ranging from immediate concerns blocking progress today to major obstacles in exploratory nanotechnologies, as described below:
· Thorough validation and test despite enormous complexity.
· Tolerance and prediction of hardware failures.
· Correct circuit operation in emerging nanotechnologies prone to imperfections.
Prof. Subhasish Mitra leads the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University. Before joining Stanford, he was a Principal Engineer at Intel Corporation.
Prof. Mitra’s research interests include robust system design, VLSI design, CAD, validation and test, and emerging nanotechnologies. His X-Compact technique for test compression has been used in more than 50 Intel products, and has influenced major CAD tools.The IFRA technology for post-silicon validation, created jointly with his student, was characterized as “a breakthrough” in the Communications of the ACM. His work on the first demonstration of imperfection-immune carbon nanotube VLSI circuits, jointly with his students and collaborators, was selected by the National Science Foundation as a Research Highlight to the US Congress, and was highlighted as “a significant breakthrough” by the Semiconductor Research Corporation and the MIT Technology Review. Prof. Mitra’s major honors include the Presidential Early Career Award for Scientists and Engineers, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA Outstanding New Faculty Award, IEEE CAS/CEDA Pederson Award for the IEEE Transactions on CAD Best Paper, IEEE/ACM Design Automation Conference Best Paper Award, Terman Fellowship, and the Intel Achievement Award, Intel’s highest corporate honor. Prof. Mitra also serves as an invited member on DARPA’s Information Science and Technology Study Group.
Dec
17, 2010, Afternoon Session (parallel with Tutorial - III)
Automated bug localization for software
programs: Approaches and Recent Directions
Ansuman Banerjee
Assistant Professor, Advanced Computing and Microelectronics Unit
Indian Statistical Institute- Kolkata
Debugging denotes the process of detecting root causes of unexpected observable behavior in programs (such as a program crash, an unexpected output value being produced or an assertion violation). Debugging program errors is a difficult process, and often takes a significant fraction of the time in the program development stage. Even today, debugging remains much of a manual activity, with the actual debugging time dependent on the size and complexity of the program being debugged, the nature of manifestation of the bug and the level of familiarity and expertise of the programmer. The standard practice of debugging till date in the software community is to manually inspect the execution trace exhibiting the bug inside a debugger and try and locate the error cause(s) from an observed error. In the past decade, there have been several attempts to automate the debugging activity by fully automated / semi-automated formal analysis of the program and/or the failed execution trace for software programs. This tutorial will discuss program analysis techniques used in debugging and explore the delicate connections between debugging and testing in the overall task of validating software. Moreover, since any deployed software undergoes changes in its lifetime, there is a need for debugging methods which can take the software evolution into account. This talk will discuss a few recent activities in this direction.
Ansuman Banerjee is an Assistant Professor at the Advanced Computing and Microelectronics Unit, Indian Statistical Institute Kolkata. His research interests include design automation for embedded systems, hardware/software verification, VLSI CAD, and automata theory. Currently, his research objective is focused on developing tools, techniques and methodologies for specification analysis, automated software debugging, functional test generation and formal / semi-formal verification for embedded systems. Ansuman received his B.E. from Jadavpur University, and M.S. and Ph.D. degrees from the Indian Institute of Technology Kharagpur -- all in Computer Science. Prior to joining Indian Statistical Institute, he spent about 6 months at the National University of Singapore as a research fellow and about four years at Interra Systems India Pvt. Ltd.He has published one book chapter and more than 30 research articles in premier journals and conferences. His research has been recognized by several awards including the Young Scientist Award from the Indian Science Congress Association, the Innovative Dissertation Award from the Indian National Academy of Engineering, best thesis award nominations from the Department of Computer Science and Engineering, IIT Kharagpur and an honorable research contribution award from VLSI 2005. Dr. Banerjee currently serves as a reviewer of the Design Automation Conference (DAC) and the VLSI conference and as a program committee member of INDICON 2010.