V.A. Vashchenko

"System level and hot plug-in ESD specs and solutions"
University of Central Florida HEC 101 01/ 23 from 12:30 to 2pm




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Abstract:

Presentation provides a general level overview for the specific of
 system level Electrostatic Discharge (ESD) protection specification,
test and design methodologies followed by review of the product cases
and new ESD devices developedfor applications with system spec level
pins. Review of physical
 principles of new high voltage lateral PNP transistor, two-stage PNP
transistor, dual direction devices is presented in support of IEC and
ISO standards ,
custom hot plug-in and automotive specifications. Finally, Human Metal Model
(HMM) wafer level tools are described as a future methodology trend to
support the device level design of the system solution.


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Bio of Dr. Vladislav Vashchenko
Dr. Vladislav Vashchenko received MS, Engineer-Physicist (1986) followed
by Ph.D. in Physics of Semiconductors (1990) from Moscow Institute
of Physics and Technology for the study of self-organization phenomena
in semiconductor structures under breakdown and injection. He was
awarded the degree Doctor of Science in Microelectronics (1997)
(similar to Habilitation in Germany) for the cycle of studies of
physical limitation of safe operating area in discrete power and
microwave GaAs and Si devices, developed test methods for local
structural defects detection and solutions of the reliability problems.
He joined National Semiconductor Corp. in 2000. Since 2006 he is a
technical leader and manager of the process development ESD group. His
group focus is corporate ESD development for new processes and lead
products involving a wide spectrum of the experimental and numerical
simulation tools.
He also acts as one of the leaders in several university projects the
project with IMEC. His current research interests are focused on the
design of ESD solutions, power devices, reliability, ESD compact models,
and innovation of integrated galvanic isolation using silicon light
emission structures. He is a member of technical committees for IRPS and
EOSESD Symposiums. His studies regularly presented in major device
research forums. He is author of over 80 research papers, over 100 U.S.
patents and co-authored book Physical limitation of semiconductor
devices.



Regards,
Slavica Malobabic,
University of Central Florida, PhD student,
IEEE EDS Chapter Chair,
321 609 1851
smalobabic@ieee.org