It has been quite a while since silicon
based CMOS scalability was questioned in terms of both physical
limit and engineering limit. Despite several good reasons for
pessimistic forecast of CMOS scaling, it is the fact that the
progress is still in line with ITRS roadmap at this moment. This
talk will discuss the progress made up to now for such CMOS scaling
in drive current improvement and suppression of off current of
MOSFET, with introductions of new structures, new materials for
channel, gate insulator and gate electrode. Further discussed
will be a variety of revolutionary nanoelectronics devices such
as nanowires/nanotubes devices, new materials based non-volatile
memory, and other emerging research interest on the horizon, followed
by looking into such candidates from future integrated electronics
point of view.
Professor
Yoshio Nishi received the BS in Materials Science and Engineering
from Waseda University and the PhD in Electronics Engineering
from University of Tokyo. He joined Toshiba Corporation in 1962,
working in the areas of semiconductor materials and processes.
He also worked in the areas of MNOS nonvolatile memory, silicon
on sapphire (SOS) based device research and memory technology
R&D. Later, he managed a group in the Semiconductor Device
Engineering Laboratory and developed the world’s first 1Mbit
CMOS DRAM, 256Kbit SRAM and EPROM. In 1986, he joined Hewlett-Packard
as Director of the Silicon Process Lab, and later the Center Director
for ICBD R&D. In 1996, he joined Texas Instruments Inc., as
Senior Vice President and Director of R&D. In 2002, he joined
Stanford University as Professor of Electrical Engineering, where
he currently serves as Director of the Stanford Nanofabrication
Facility and Research Director of the Center for Integrated Systems.
His research interests at Stanford are quantum confined high mobility
channel, metal gate work function engineering, and nonvolatile
nanowire based memory devices. Professor Nishi has published over
120 papers, co-authored several books and holds more than 50 patents
including Schottky source drain MOSFET. He is a Fellow of IEEE
and the recipient of IEEE Jack Morton Award (1995) and IEEE Robert
Noyce Medal (2002).
