In this talk, we will discuss variability challenges in VLSI design and our recent research efforts on variation-tolerant design techniques. Variability in circuit delay, chip temperature, and transistor aging have imposed a large amount of pessimistic margins in frequency, voltage, and device size, which has severely undermined gains from various boundary-pushing efforts. We will present (1) a low-overhead, in-situ, within-a-cycle error detection and correction technique that can operate at near/sub-threshold voltage, (2) ultra-compact thermal sensor circuits enabling 10X denser on-chip thermal sensing, (3) self-testing circuits and frameworks for in-field & in-situ aging monitoring in pipeline and SRAM register files. Several test chip measurement results will be presented.