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Technical
Seminar Distinguished
Lecturer Series |
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Mixed-Mode ESD Protection Simulation-Design for Integrated Circuits
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DATE/TIME
Friday, April 11, 2003 ( 4:30pm to 6:00pm)
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PLACE
Glover Bldg. Rm. 201 (CSU,
Fort Collins, CO)
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ABSTRACT
ESD (Electro-Static Discharge) induced failure becomes a major IC reliability problem as semiconductor IC technologies
migrate into the VDSM (very-deep-sub-micron) ULSI (ultra large scale
integration) regime. On-chip ESD protection circuitry is required to protect IC chips
against ESD damages. Particularly, ESD design for mixed-signal
& RF IC is a new challenge to IC designers. Currently,
trial-and-error approaches still dominate in ESD design practices, largely due to the lack
of predictive ESD simulation capacity. This talk will outline the
principles of ESD protection circuit design and discuss a new mixed-mode ESD
simulation-design methodology developed at the Integrated Electronics
Laboratory, Illinois Institute of Technology. Practical ESD protection
circuit design examples will be provided. This lecture aims to assist IC circuit
designers in dealing with real-world ESD protection circuit design
problems. Those who are interested in more details are referred to a short
course, ECE723 Advanced ESD Protection Design For Integrated Circuits,
offered by the Department of ECE at the Illinois Institute of
Technology and the University of California at Berkeley Extension
Short Course Series. |
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PRESENTATION SLIDES
pdf |
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REFERENCE
ON-CHIP ESD PROTECTION FOR INTEGRATED CIRCUITS: An IC Design
Perspective, by Albert Wang, Kluwer Academic
Publishers, 2002, ISBN: 0-7923-7647-1. |
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PROF. ALBERT WANG (Illinois Institute of Technology, Chicago, IL)
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Albert Wang received the BSEE degree from Tsinghua University,
China, in 1985 and the PhDEE degree from The
State University of New York at Buffalo in
1995. He was with National Semiconductor Corporation until 1998
when he joined the Faculty of Electrical and
Computer Engineering of the Illinois Institute of
Technology, where he is currently directing the Integrated Electronics
Laboratory. His research interests center on analog/mixed-signal/RF ICs, advanced
on-chip ESD
protection, IC CAD and modeling, SoCs and semiconductor devices,
etc. He received the CAREER Award from the National Science
Foundation in 2002. He is the author of the
book "On-Chip ESD Protection for Integrated Circuits" (Kluwer, 2002) and more than sixty papers in the
field, and holds several U.S. patents. |
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He is an Editor for the IEEE
Electron Device Letters and an Associate Editor
for the IEEE Transactions on Circuits and Systems II. He is an IEEE Distinguished Lecturer for the Electron Devices Society and the
Solid-State Circuits Society, an IEEE EDS AdCom
Member, Vice Chair of EDS Regions and Chapters
Committee for North America West and a Member of the
EDS VLSI Technology and Circuits Committee. He serves as Technical
Program Committee Member, Sub-Committee Chair and Session
Chair for many conferences, e.g., IEEE CICC, RFIC, APC-CAS, ASP-DAC, etc.
He is an IEEE Senior
Member, a frequent speaker at various industrial, academic, and
international
forums and a frequent consultant to the IC industry. |
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Website
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