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Technical
Seminar |
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Introduction to On-Chip Copper/Low-K Interconnects
& Electromigration Fundamentals
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DATE/TIME
Friday, September 12, 2003
(4:30pm to 6:00pm)
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PLACE
Engineering
Bldg. B4 (basement) (CSU,
Fort Collins, CO)
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ABSTRACT The relentless drive toward higher speed,
higher density, and more reliable silicon IC's has necessitated
significant advances in on-chip interconnect technologies.
Since 1998, Damascene copper was introduced to replace conventional
aluminum alloys in leading-edge semiconductor manufacturing.
Continued advances in copper technology have introduced dielectrics
with progressively lower dielectric constants (low-K) for reduced
wiring capacitance. This tutorial presents basic motivations for
integrating Damascene copper and low-K dielectrics and highlights key
process integration and manufacturing issues associated with these new
technologies. Additionally, it will explain electromigration
fundamentals to provide a better appreciation of interconnect
reliability. |
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PRESENTATION SLIDES
pdf |
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Ph.D. THESIS ON COPPER/LOW-K INTERCONNECTS
pdf |
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ALVIN LOKE, Ph.D. (Agilent
Technologies, Fort Collins, CO)
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Alvin Loke received his B.A.Sc. (Eng. Physics) degree with highest honors from the University of British Columbia,
Vancouver, Canada, in 1992, and the M.S.E.E. and Ph.D.E.E. degrees from Stanford University, Stanford, CA, in 1994 and
1999 respectively. He was a recipient of the Canadian NSERC 1967 Graduate
Scholarship. While at Stanford, his research focused on
interconnect process integration issues with copper and low-K polymer
dielectrics. Dr. Loke has authored and co-authored over 20 technical
publications. He held internships at Texas
Instruments (Dallas, TX), Motorola ( Austin, TX), and at Sumitomo
Electric Industries (Osaka, Japan). In 1998, he joined Hewlett-Packard Laboratories,
Palo Alto, CA where he was involved in process integration of deep
submicron ferroelectric memory for embedded applications. |
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In
1999, when Agilent Technologies was spun off from Hewlett-Packard, he took a
two-year assignment in Chartered Silicon Partners, Singapore, as Senior
Process Integration Engineer engaged in copper and local interconnect module integration. In 2001, he returned to Fort Collins, CO,
where he is presently Design Engineer developing mixed-signal phase-locked
loop circuits for embedded SerDes I/O and ASIC clock skew applications. |
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TIN TIN WEE (Chartered Semiconductor Manufacturing, Singapore)
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Tin Tin Wee received her B.
Tech. (Electronics Eng.) from the National University of Singapore,
Singapore, in 1999. Prior to receiving her B. Tech., she was an
Associate Engineer at International Video Products, Singapore, where
she involved in RF test, measurement, and failure analysis of consumer
video electronics. In 1996, she joined Chartered Semiconductor
Manufacturing, Singapore, as Process Integration Engineer where she
was engaged in multiple aspects of 0.25um, 0.18um, and 0.15um
technology development and transfer. Activities included SRAM
development, yield enhancement, and most recently, copper and local
interconnect module integration. Ms. Wee returned to the
National University of Singapore to study circuits and systems, and
completed her M.S.E.E. degree in 2001. |
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She now resides in Fort
Collins, CO, as a self-taught woodworker and wood jewelry artisan at
Trimble Court Artisan Co-op. Ms. Wee is presently seeking a
technical opportunity in circuit design or technology
development. |
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