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Technical
Seminar |
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Analog Adventures in Digital Chip Testing
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DATE/TIME
Tuesday, April 19, 2005
(4:30pm to 6:00pm)
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PLACE
Bldg. 1 Auditorium (Agilent Technologies,
Fort Collins, CO)
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DIRECTIONS
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Non-Agilent/HP/Intel
Attendees: Please arrive punctually at 4:15pm as you will
need to be escorted to the seminar
room. We appreciate a courtesy RSVP to bob_barnes@agilent.com
to expedite sign-in and to help us with a headcount estimate for
food/drinks. |
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From I-25, take Harmony Road Exit (Exit
265) westbound, and enter Agilent/HP campus on right. Agilent/HP
campus is on the NE corner of Harmony Road and Ziegler Road.
Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to
Auditorium. |
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COST
Free. As always, pizza &
drinks will be provided. |
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ABSTRACT
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As the operating frequencies of digital
integrated circuits continue to rise while the power supply voltages and
signal swings continue to fall, common notions of designing and testing
digital chips are being challenged. One aspect of this new situation
is that while traditional digital chip testing is still necessary, it is
not sufficient to assure acceptable quality levels. Indeed, many
circuit design marginalities and IC process defects manifest themselves in
the analog realm and must be dealt with there rather than with digital
methods. |
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This presentation briefly reviews digital
testing, then explores several problems with these techniques that are
forcing analog test concepts to be employed. Special attention is
paid to the complexity of at-speed testing in general and high-speed
serial I/O testing in particular. Some possible directions for both
off-chip and on-chip test hardware and methods are surveyed, and some
recent results from the lab are presented. |
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PRESENTATION SLIDES
pdf |
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JEFF
REARICK (Agilent
Technologies, Fort Collins, CO)
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Jeff Rearick joined Hewlett Packard in 1984
after earning his BSEE from Purdue University, Lafayette, IN. His
early work on generating manufacturing tests for large digital chips led
him toward the R&D lab and into the CAD tools group to work on design
and test automation software. During this time, Mr. Rearick received
an HP Fellowship to attend the University of Illinois, Urbana-Champaign,
IL, at which he earned his MSEE in 1993. He returned to continue his
test work by focusing on Design-For-Test methodologies and circuits for HP
Precision Architecture processors and support chips, for which he has
earned over 20 patents and many publications. Since being spun-off
from HP into Agilent Technologies, Mr. Rearick has continued his test work
on large high-performance ASICs, leading to recent work on high-speed I/O
testing (some of which became IEEE Stardard 1149.6, for which he served on
the working group) as well as embedded analog instrumentation. |
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PHOTOS
Courtesy of Bob Barnes |
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