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Technical
Seminar |
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Exceeding the Speed Limit: Challenges and Solutions
to the Support of Serial 10 Gigabit Ethernet over Backplane
Interconnects |
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DATE/TIME
Friday, March 10, 2006
(10:00am to 11:30am) NOTE MORNING TIME!!! |
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PLACE
Bldg. 1 Auditorium (Avago
Technologies, Fort Collins, CO, formerly Agilent Technologies) |
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DIRECTIONS
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Non-Avago
Attendees: Please arrive punctually at 9:45am as you will
need to be escorted to the seminar
room. RSVP to
bob.barnes@avagotech.com
to expedite sign-in and to help us with a headcount estimate for
food/drinks. |
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From I-25, take Harmony Road Exit (Exit
265) westbound, and enter Agilent/HP campus on right. Avago/HP/Intel
campus is on the NE corner of Harmony Road and Ziegler Road.
Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to
Auditorium. |
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COST
Free. As always, food &
drinks will be provided. |
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ABSTRACT
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10 Gb/s serial operation over
an electrical backplane has been a focus of industry attention over the
past several years. The definition of a 10 Gb/s serial interface (SerDes)
is heavily influenced by the environment to which it is targeted.
Enhancements to current backplane design practice (board material
selection, stub reduction techniques, etc.) were considered
carefully to balance the cost of the backplane, line cards, and fabric
cards with the cost, complexity, and power of the SerDes. Even
with considerable improvements in the backplane interconnect
performance, robust operation at 10 Gb/s proves to be a non-trivial
undertaking.
The IEEE P802.3ap (Backplane Ethernet) Task Force, formed in May
2004, has been working on the definition of specifications for serial 10
Gigabit Ethernet operation over an electrical backplane (10GBASE-KR).
This presentation will highlight the technical challenges presented
by the backplane interconnect and introduce the SerDes architecture
proposed to address those challenges. |
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PRESENTATION SLIDES
pdf |
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ADAM HEALEY (Agere
Systems, Andover, MA)
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Adam Healey is a Consulting
Member of Technical Staff at Agere Systems and is responsible for the
definition of subsystems and components required for access and
enterprise networks. He joined Lucent Microelectronics / Agere
Systems in 2000. Prior to joining Agere Systems, he worked for
seven years are University of New Hampshire's InterOperability Lab where
he developed many of the test procedures and systems used to verify
interoperability, performance, and compliance to standards of 10, 100,
and 1000 Mb/s electrical and optical links. Adam is a member of
IEEE and contributes to the development of international standards as a
member of IEEE 802.3 working group. He currently serves as Chair of the
IEEE P802.3ap Backplane Ethernet Task Force. He received the BS
and MS degrees in electrical engineering from the University of New
Hampshire, Durham, NH. |
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PHOTOS
Courtesy of Tin Tin Wee |
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